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AT17C256A-10JC PDF预览

AT17C256A-10JC

更新时间: 2024-11-23 22:47:55
品牌 Logo 应用领域
爱特美尔 - ATMEL 存储内存集成电路异步传输模式ATM可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
11页 162K
描述
FPGA Configuration EEPROM

AT17C256A-10JC 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:QLCC包装说明:QCCJ, LDCC20,.4SQ
针数:20Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.89Is Samacsys:N
最长访问时间:50 nsJESD-30 代码:S-PQCC-J20
JESD-609代码:e0长度:8.9662 mm
内存密度:262144 bit内存集成电路类型:CONFIGURATION MEMORY
内存宽度:1湿度敏感等级:2
功能数量:1端子数量:20
字数:262144 words字数代码:256000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:256KX1
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC20,.4SQ封装形状:SQUARE
封装形式:CHIP CARRIER并行/串行:SERIAL
峰值回流温度(摄氏度):225电源:5 V
认证状态:Not Qualified座面最大高度:4.57 mm
最大待机电流:0.000075 A子类别:EEPROMs
最大压摆率:0.01 mA最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:8.9662 mmBase Number Matches:1

AT17C256A-10JC 数据手册

 浏览型号AT17C256A-10JC的Datasheet PDF文件第2页浏览型号AT17C256A-10JC的Datasheet PDF文件第3页浏览型号AT17C256A-10JC的Datasheet PDF文件第4页浏览型号AT17C256A-10JC的Datasheet PDF文件第5页浏览型号AT17C256A-10JC的Datasheet PDF文件第6页浏览型号AT17C256A-10JC的Datasheet PDF文件第7页 
Features  
EE Programmable 65,536 x 1, 131,072 x 1 and 262,144 x 1 bit Serial Memories Designed  
to Store Configuration Programs for Programmable Gate Arrays  
Simple Interface to SRAM FPGAs Requires Only One User I/O Pin  
Able to Configure with EPF6000 and EPF8000, Flex 10K FPGAs  
Cascadable To Support Additional Configurations or Future Higher-Density Arrays  
(17C128/256 only)  
Low-Power CMOS EEPROM Process  
Programmable Reset Polarity  
Available in Industry-Standard Pin-Compatible PLCC Package  
In-System Programmable via 2-Wire Bus  
Emulation of 24CXX Serial EEPROMs  
FPGA  
Available in 3.3V and 5V Versions  
Configuration  
EEPROM  
Description  
The AT17C65/128/256A and AT17LV65/128/256A (AT17A Series) FPGA Configura-  
tion EEPROMS (Configurator) provide an easy-to-use, cost-effective configuration  
memory for Field Programmable Gate Arrays. The AT17A Series is packaged in the  
popular 20-pin PLCC. The AT17A Series family uses a simple serial-access provides  
to configure one or more FPGA devices. The AT17A Series organization supplies  
enough memory to configure one or multiple smaller FPGAs. Using a special feature  
of the AT17A Series, the user can select the polarity of the reset function by program-  
ming a special EEPROM bit.  
65K, 128K and 256K  
AT17CxxxA  
AT17LVxxxA  
The AT17A Series is pin compatible with the industry standard configurator, and can  
be programmed with industry standard programmers.  
Pin Configurations  
20-Pin PLCC  
CLK (DCLK)  
4
5
6
7
8
18 SER_EN  
17 NC  
NC  
NC  
NC  
16 NC  
15 NC  
RESET/OE (RESET/OE)  
14 NC  
Rev. 0996A–07/98  

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