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AT17C010-10JC PDF预览

AT17C010-10JC

更新时间: 2024-10-25 22:39:15
品牌 Logo 应用领域
爱特美尔 - ATMEL 存储内存集成电路异步传输模式ATM可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
9页 117K
描述
FPGA Configuration E2PROM Memory

AT17C010-10JC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QLCC包装说明:QCCJ, LDCC20,.4SQ
针数:20Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.82JESD-30 代码:S-PQCC-J20
JESD-609代码:e0长度:8.9662 mm
内存密度:1048576 bit内存集成电路类型:CONFIGURATION MEMORY
内存宽度:1湿度敏感等级:2
功能数量:1端子数量:20
字数:1048576 words字数代码:1000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:1MX1
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC20,.4SQ封装形状:SQUARE
封装形式:CHIP CARRIER并行/串行:SERIAL
峰值回流温度(摄氏度):225电源:5 V
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:EEPROMs最大压摆率:0.01 mA
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:8.9662 mm
写保护:HARDWAREBase Number Matches:1

AT17C010-10JC 数据手册

 浏览型号AT17C010-10JC的Datasheet PDF文件第2页浏览型号AT17C010-10JC的Datasheet PDF文件第3页浏览型号AT17C010-10JC的Datasheet PDF文件第4页浏览型号AT17C010-10JC的Datasheet PDF文件第5页浏览型号AT17C010-10JC的Datasheet PDF文件第6页浏览型号AT17C010-10JC的Datasheet PDF文件第7页 
Features  
E2 Programmable 524,288 x 1 and 1,048,576 x 1 bit Serial Memories Designed To Store  
Configuration Programs For Field Programmable Gate Arrays (FPGA)  
Simple Interface to SRAM FPGAs  
Compatible With Atmel AT6000, AT40K FPGAs, Altera EPF8K, EPF10K,  
EPF6K FPGAs, ORCA FPGAs, Xilinx XC3000, XC4000, XC5200 FPGAs, Motorola  
MPA1000 FPGAs  
Cascadable To Support Additional Configurations or Future Higher-density Arrays  
Low-power CMOS EEPROM Process  
Programmable Reset Polarity  
Available In PLCC Package (Pin Compatable across Product Family)  
In-System Programmable Via 2-Wire Bus  
Emulation of 24CXX Serial EPROMs  
FPGA  
Configuration  
E2PROM  
Memory  
Available in 3.3V ± 10% LV and 5V Versions  
System Friendly READY Pin  
Description  
The AT17C512/010 and AT17LV512/010 (high-density AT17 Series) FPGA Configu-  
ration EEPROMs (Configurators) provide an easy-to-use, cost-effective configuration  
memory for Field Programmable Gate Arrays. The high-density AT17 Series is pack-  
aged in the popular 20-pin PLCC. The high-density AT17 Series family uses a simple  
serial-access procedure to configure one or more FPGA devices. The high-density  
AT17 Series organization supplies enough memory to configure one or multiple  
smaller FPGAs. The user can select the polarity of the reset function by programming  
one EEPROM byte. The devices also support a write protection mode and a system  
friendly READY pin, which signifies a “good” power level to the device and can be  
used to ensure reliable system power-up.  
512K and 1M  
AT17C512  
AT17LV512  
AT17C010  
AT17LV010  
The high-density AT17 Series can be programmed with industry-standard program-  
mers, and the Atmel ATDH2200 Programming board.  
Pin Configurations  
20-Pin PLCC  
D
A
T
A
V
C
C
N
C
N
C
N
C
3
2
1
20 19  
18  
CLK  
WP1  
4
5
6
7
8
NC  
17  
16  
15  
14  
SER_EN  
NC  
RESET/OE  
WP2  
READY  
CEO  
CE  
9
10 11 12 13  
N
C
G
N
D
N
C
N
C
N
C
Rev. 0944A-A–12/97  

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