Datasheet > 逻辑 > 时钟驱动器> ASM5P23S08A-1-16-TT

ASM5P23S08A-1-16-TT

更新时间： 2024-11-23 23:04:23

品牌	Logo	应用领域
ALSC		逻辑集成电路光电二极管驱动
页数	文件大小	规格书
18页	395K
描述
3.3V Zero Delay Buffer

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September 2005

rev 1.4

ASM5P23S08A

3.3V ‘SpreadTrak’ Zero Delay Buffer

General Features

The ASM5P23S08A has two banks of four outputs each,

which can be controlled by the select inputs as shown in

the Select Input Decoding Table. The select input also

allows the input clock to be directly applied to the outputs

for chip and system testing purposes.

•

Zero input - output propagation delay, adjustable by

capacitive load on FBK input.

•

Multiple configurations

Configurations” Table.

Refer “ASM5P23S08A

•

Input frequency range: 15MHz to 133MHz

Multiple low-skew outputs.

o Output-output skew less than 200pS.

o Device-device skew less than 700pS.

Two banks of four outputs, three-stateable by two

select inputs.

Multiple ASM5P23S08A devices can accept the same input

clock and distribute it. In this case the skew between the

outputs of the two devices is guaranteed to be less than

700pS.

The ASM5P23S08A is available in five different

configurations (Refer “ASM5P23S08A Configurations

Table). The ASM5P23S08A-1 is the base part, where the

output frequencies equal the reference if there is no

counter in the feedback path. The ASM5P23S08A-1H is

the high-drive version of the -1 and the rise and fall times

on this device are faster.

•

Less than 200pS Cycle-to-cycle jitter

(-1, -1H, -2, -3, -4, -5H).

Available in 16 pin SOIC and TSSOP Packages.

3.3V operation.

Advanced 0.35µ CMOS technology.

Industrial temperature available.

‘SpreadTrak’.

•

The ASM5P23S08A-2 allows the user to obtain 2X and 1X

frequencies on each output bank. The exact configuration

and output frequencies depends on which output drives the

feedback pin. The ASM5P23S08A-3 allows the user to

obtain 4X and 2X frequencies on the outputs.

Functional Description

ASM5P23S08A is a versatile, 3.3V zero-delay buffer

designed to distribute high-speed clocks. It is available in a

16 pin package. The part has an on-chip PLL, which locks

to an input clock, presented on the REF pin. The PLL

feedback is required to be driven to FBK pin, and can be

obtained from one of the outputs. The input-to-output

propagation delay is guaranteed to be less than 250pS,

and the output-to-output skew is guaranteed to be less than

200pS.

The ASM5P23S08A-4 enables the user to obtain 2X clocks

on all outputs. Thus, the part is extremely versatile, and

can be used in a variety of applications.

The ASM5P23S08A-5H is a high-drive version with REF/2

on both banks

Alliance Semiconductor

2575 Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com

Notice: The information in this document is subject to change without notice.

12 3 4 5 6 7...18

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与ASM5P23S08A-1-16-TT相关器件

型号	品牌	获取价格	描述	数据表
ASM5P23S08A-1H-16-SR	ALSC	获取价格	3.3V Zero Delay Buffer
ASM5P23S08A-1H-16-ST	ALSC	获取价格	3.3V Zero Delay Buffer
ASM5P23S08A-1H-16-TR	ALSC	获取价格	3.3V Zero Delay Buffer
ASM5P23S08A-1H-16-TT	ALSC	获取价格	3.3V Zero Delay Buffer
ASM5P23S08A-2-16-SR	ALSC	获取价格	3.3V Zero Delay Buffer
ASM5P23S08A-2-16-ST	ALSC	获取价格	3.3V Zero Delay Buffer
ASM5P23S08A-2-16-TR	ALSC	获取价格	3.3V Zero Delay Buffer
ASM5P23S08A-2-16-TT	ALSC	获取价格	3.3V Zero Delay Buffer
ASM5P23S08A-3-16-SR	ALSC	获取价格	3.3V Zero Delay Buffer
ASM5P23S08A-3-16-ST	ALSC	获取价格	3.3V Zero Delay Buffer

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