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ASM5P23S04AF-1-08-SR PDF预览

ASM5P23S04AF-1-08-SR

更新时间： 2024-11-24 06:38:15
品牌 Logo 应用领域
PULSECORE 时钟驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
15页 412K
描述
3.3V ‘SpreadTrak’ Zero Delay Buffer

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ASM5P23S04AF-1-08-SR 技术参数

是否Rohs认证：符合生命周期：Obsolete
包装说明：0.150 INCH, ROHS COMPLIANT, SOIC-8Reach Compliance Code：unknown
风险等级：5.63Is Samacsys：N
系列：23S输入调节：STANDARD
JESD-30 代码：R-PDSO-G8JESD-609代码：e3/e6
长度：4.9 mm逻辑集成电路类型：PLL BASED CLOCK DRIVER
功能数量：1反相输出次数：
端子数量：8实输出次数：4
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.2 ns座面最大高度：1.75 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：MATTE TIN/TIN BISMUTH端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40宽度：3.91 mm
最小 fmax：133 MHzBase Number Matches：1

ASM5P23S04AF-1-08-SR 数据手册

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November 2006  
rev 1.4  
ASMP5P23S04A  
3.3V ‘SpreadTrak’ Zero Delay Buffer  
Features  
FBK pin, and can be obtained from one of the outputs. The  
input-to-output propagation delay is guaranteed to be less  
than 250 pS, and the output-to-output skew is guaranteed  
to be less than 200 pS.  
•
Zero input - output propagation delay, adjustable  
by capacitive load on FBK input.  
Multiple configurations - Refer “ASM5P23S04A  
Configurations Table”.  
•
•
•
•
•
•
•
Input frequency range: 15 MHz to 133 MHz  
Multiple low-skew outputs.  
Output-output skew less than 200 pS.  
Device-device skew less than 500 pS.  
Two banks of two outputs each.  
The ASM5P23S04A has two banks of two outputs each.  
Multiple ASM5P23S04A devices can accept the same input  
clock and distribute it. In this case the skew between the  
outputs of the two devices is guaranteed to be less than  
500 pS.  
Less than 200 pS cycle-to-cycle jitter  
•
(-1, -1H, -2, -2H).  
The ASM5P23S04A is available in two different  
configurations (Refer “ASM5P23S04A Configurations  
Table). The ASM5P23S04A-1 is the base part, where the  
output frequencies equal the reference if there is no  
counter in the feedback path. The ASM5P23S04A-1H is  
the high-drive version of the -1 and the rise and fall times  
on this device are much faster.  
•
Available in space saving, 8-pin 150-mil SOIC  
package.  
3.3V operation.  
Advanced 0.35µ CMOS technology.  
Industrial temperature available.  
‘SpreadTrak’.  
•
•
•
•
The ASM5P23S04A-2 allows the user to obtain Ref and  
1/2X frequencies on each output bank. The exact  
configuration and output frequencies depend on which  
output drives the feedback pin.  
Functional Description  
ASM5P23S04A is a versatile, 3.3V zero-delay buffer  
designed to distribute high-speed clocks in PC,  
workstation, datacom, telecom and other high-performance  
applications. It is available in a 8-pin package. The part has  
an on-chip PLL, which locks to an input clock, presented on  
the REF pin. The PLL feedback is required to be driven to  
The ASM5P23S04A-2H is a high-drive version with REF/2  
on both banks.  
Block Diagram  
FBK  
CLKA1  
PLL  
REF  
CLKA2  
/2  
Extra Divider (-2)  
CLKB1  
CLKB2  
PulseCore Semiconductor Corporation  
1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018  
www.pulsecoresemi.com  
Notice: The information in this document is subject to change without notice.  
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