Datasheet > 逻辑 > 时钟驱动器> ASM5P23S04AF-1-08-ST

ASM5P23S04AF-1-08-ST

更新时间： 2024-11-23 22:31:19

品牌	Logo	应用领域
ALSC		时钟驱动器逻辑集成电路光电二极管
页数	文件大小	规格书
15页	348K
描述
3.3V SpreadTrak Zero Delay Buffer

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

ASM5P23S04AF-1-08-ST 数据手册

浏览型号ASM5P23S04AF-1-08-ST的Datasheet PDF文件第2页

浏览型号ASM5P23S04AF-1-08-ST的Datasheet PDF文件第3页

浏览型号ASM5P23S04AF-1-08-ST的Datasheet PDF文件第4页

浏览型号ASM5P23S04AF-1-08-ST的Datasheet PDF文件第5页

浏览型号ASM5P23S04AF-1-08-ST的Datasheet PDF文件第6页

浏览型号ASM5P23S04AF-1-08-ST的Datasheet PDF文件第7页

September 2005

rev 1.3

ASM5P23S04A

3.3V ‘SpreadTrak’ Zero Delay Buffer

Features

the REF pin. The PLL feedback is required to be driven to

FBK pin, and can be obtained from one of the outputs. The

input-to-output propagation delay is guaranteed to be less

than 250pS, and the output-to-output skew is guaranteed to

be less than 200pS.

Zero input - output propagation delay, adjustable

by capacitive load on FBK input.

Multiple configurations - Refer “ASM5P23S04A

Configurations Table”.

Input frequency range: 15MHz to 133MHz

Multiple low-skew outputs.

The ASM5P23S04A has two banks of two outputs each.

Multiple ASM5P23S04A devices can accept the same input

clock and distribute it. In this case the skew between the

outputs of the two devices is guaranteed to be less than

500pS.

Output-output skew less than 200pS.

Device-device skew less than 500pS.

Two banks of two outputs each.

Less than 200pS Cycle-to-cycle jitter

(-1, -1H, -2, -2H).

Available in space saving, 8 pin 150-mil SOIC

package.

3.3V operation.

Advanced 0.35µ CMOS technology.

Industrial temperature available.

‘SpreadTrak’.

The ASM5P23S04A is available in two different

configurations (Refer “ASM5P23S04A Configurations

Table). The ASM5P23S04A-1 is the base part, where the

output frequencies equal the reference if there is no

counter in the feedback path. The ASM5P23S04A-1H is

the high-drive version of the -1 and the rise and fall times

on this device are much faster.

Functional Description

The ASM5P23S04A-2 allows the user to obtain REF and

1/2X or 2X frequencies on each output bank. The exact

configuration and output frequencies depend on which

output drives the feedback pin.

ASM5P23S04A is a versatile, 3.3V zero-delay buffer

designed to distribute high-speed clocks in PC,

workstation, datacom, telecom and other high-performance

applications. It is available in a 8 pin package. The part has

an on-chip PLL, which locks to an input clock, presented on

Block Diagram

FBK

CLKA1

PLL

REF

CLKA2

Extra Divider (-2)

CLKB1

CLKB2

Alliance Semiconductor

2575 Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com

Notice: The information in this document is subject to change without notice.

12 3 4 5 6 7...15

中文翻译

下载PDF

与ASM5P23S04AF-1-08-ST相关器件

型号	品牌	获取价格	描述	数据表
ASM5P23S04AF-1H-08-SR	ALSC	获取价格	3.3V SpreadTrak Zero Delay Buffer
ASM5P23S04AF-1H-08-SR	PULSECORE	获取价格	3.3V ‘SpreadTrak’ Zero Delay Buffer
ASM5P23S04AF-1H-08-ST	ALSC	获取价格	3.3V SpreadTrak Zero Delay Buffer
ASM5P23S04AF-1H-08-ST	PULSECORE	获取价格	3.3V ‘SpreadTrak’ Zero Delay Buffer
ASM5P23S04AF-2-08-SR	PULSECORE	获取价格	3.3V ‘SpreadTrak’ Zero Delay Buffer
ASM5P23S04AF-2-08-SR	ALSC	获取价格	3.3V SpreadTrak Zero Delay Buffer
ASM5P23S04AF-2-08-ST	PULSECORE	获取价格	3.3V ‘SpreadTrak’ Zero Delay Buffer
ASM5P23S04AF-2-08-ST	ALSC	获取价格	3.3V SpreadTrak Zero Delay Buffer
ASM5P23S04AF-2H-08-SR	ALSC	获取价格	3.3V SpreadTrak Zero Delay Buffer
ASM5P23S04AF-2H-08-SR	PULSECORE	获取价格	3.3V ‘SpreadTrak’ Zero Delay Buffer

与ASM5P23S04AF-1-08-ST相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

38
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

30
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

58
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

54

产品中心

服务支持

精选活动

关于我们

帮助中心

ASM5P23S04AF-1-08-ST

ASM5P23S04AF-1-08-ST 数据手册

与ASM5P23S04AF-1-08-ST相关器件

与ASM5P23S04AF-1-08-ST相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

ASM5P23S04AF-1-08-ST

ASM5P23S04AF-1-08-ST 数据手册

与ASM5P23S04AF-1-08-ST相关器件

与ASM5P23S04AF-1-08-ST相关文章

您还可以找

您在本页遇到什么问题？