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ASM3P623S00E PDF预览

ASM3P623S00E

更新时间: 2024-11-09 06:38:11
品牌 Logo 应用领域
PULSECORE /
页数 文件大小 规格书
15页 545K
描述
Timing-Safe™ Peak EMI reduction IC

ASM3P623S00E 数据手册

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May 2008  
rev 0.5  
ASM3P623S00B/E  
Timing-Safe™ Peak EMI reduction IC  
Safe™ clock. ASM3P623S00E accepts one reference input  
and drives out eight low-skew Timing-Safe™clocks.  
General Features  
Clock distribution with Timing-Safe™ Peak EMI  
ASM3P623S00B/E has an SS% that selects 2 different  
Deviation and associated Input-Output Skew (TSKEW). Refer  
Spread Spectrum Control and Input-Output Skew table  
for details.  
Reduction  
Input frequency range: 20MHz - 50MHz  
2 different Spread Selection option  
Spread Spectrum can be turned ON/OFF  
External Input-Output Delay Control option  
Supply Voltage: 3.3V±0.3V  
ASM3P623S00E has a CLKOUT for adjusting the Input-  
Output clock delay, depending upon the value of capacitor  
connected at this pin to GND.  
Commercial and Industrial temperature range  
Packaging Information:  
ASM3P623S00B: 8 pin SOIC, and TSSOP  
ASM3P623S00E:16 pin SOIC, and TSSOP  
The First True Drop-in Solution  
ASM3P623S00B/E operates from a 3.3V supply and is  
available in two different packages, as shown in the  
ordering information table, over commercial and Industrial  
temperature range.  
Functional Description  
Application  
ASM3P623S00B/E is a versatile, 3.3V Zero-delay buffer  
designed to distribute Timing-Safe™ clocks with Peak EMI  
reduction. ASM3P623S00B is an eight-pin version, accepts  
one reference input and drives out one low-skew Timing-  
ASM3P623S00B/E is targeted for use in Displays and  
memory interface systems.  
General Block Diagram  
VDD  
DLY_CTRL  
SS%  
CLKIN  
PLL  
CLKOUT(s)*  
(Timing-Safe™)  
*For  
ASM3P623S00E -  
8 CLKOUTS  
SSON  
GND  
PulseCore Semiconductor Corporation  
1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018  
www.pulsecoresemi.com  
Notice: The information in this document is subject to change without notice.  

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