Datasheet > 微控制器和处理器 > 时钟发生器> ASM3P2508SPF-08SR

ASM3P2508SPF-08SR

更新时间： 2024-11-10 22:26:39

品牌	Logo	应用领域
ALSC		晶体时钟发生器微控制器和处理器外围集成电路光电二极管 ISM频段
页数	文件大小	规格书
7页	303K
描述
Clock Synthesizer and Frequency Generator with Peak EMI reduction

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February 2005

rev 0.4

ASM3P2508SP

Clock Synthesizer and Frequency Generator with Peak EMI reduction

Features

The ASM3P2508SP uses the most efficient and

optimized modulation profile approved by the FCC.

ASM3P2508SP modulates the output of a PLL in order to

“spread” the bandwidth of a synthesized clock, and more

importantly, decreases the peak amplitudes of its

harmonics. This results in a significantly lower system

EMI compared to the typical narrow band signal produced

by oscillators and most frequency generators. Lowering

EMI by increasing a signal’s bandwidth is called ‘spread

spectrum clock generation’ (SSCG).

Dual PLL based Architecture

Operates with a 3.3V ±0.3V supply.

Generates an EMI optimized Spread Spectrum

PCI Clock output

Generates a high accuracy non Spread T1 clock of

±25ppm accuracy.

Generates a non spread system reference clock

Low power CMOS design.

Input frequency: 25 MHz.

Outputs:

In addition to the SSCG output, ASM3P2508SP

generates two high accuracy clock signals -

T1 Clock @ 25.00MHz with +/- 25ppm stability, and a

20MHz Sys_ REF_CLK.

Sys_ REF_CLK: 20 MHz

T1 Clock: 25 MHz (±25 ppm)

PCI_CLK: 33.33MHz Spread Spectrum

Frequency deviation: -0.5% (Typ).

Available in 8L SOIC Package.

Applications

The ASM3P2508SP is targeted towards Consumer,

Industrial, Data and Telecommunications applications.

Product Description

The ASM3P2508SP is a versatile Dual PLL based Clock

Synthesizer and Frequency Generator optimised and

designed specifically for three clock frequencies. The

Key Specifications

Description

Supply voltages

Input Frequency

Cycle-to-Cycle Jitter

Output Duty Cycle

Output Rise and Fall Time

SSC Modulation Rate

SSC Frequency Deviation

Specification

V_DD= 3.3V ±0.3V

25 MHz

175 pS ( Max)

45/55%

1.1 nS (Max)

30KHz (Typ)

-0.5% (Typ)

PCI_CLK

output

from

ASM3P2508SP

reduces

electromagnetic interference (EMI) at the clock source,

allowing system wide reduction of EMI of all clock

dependent signals. ASM3P2508SP allows significant

system cost savings by reducing the number of circuit

board layers, ferrite beads

traditionally required to pass EMI regulations.

shielding that are

Block Diagram

PWRDNB

V_DD

Output

Divider

T1_CLK

Input

PLL 1

Sys_REF_CLK

Divider

XIN/CLKIN

XOUT

Osc

PCI_CLK

PLL 2

Output

Divider

Modulation

V_SS

Alliance Semiconductor

2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com

Notice: The information in this document is subject to change without notice.

12 3 4 5 6 7

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与ASM3P2508SPF-08SR相关器件

型号	品牌	获取价格	描述	数据表
ASM3P2508SPF-08ST	ALSC	获取价格	Clock Synthesizer and Frequency Generator with Peak EMI reduction
ASM3P2508SPF-08ST	PULSECORE	获取价格	Clock Generator, 33.33MHz, CMOS, PDSO8, 0.150 INCH, LEAD FREE, SOIC-8
ASM3P2531A	ALSC	获取价格	Low Frequency EMI Reduction
ASM3P2531A	PULSECORE	获取价格	Low Frequency EMI Reduction
ASM3P2531A-08SR	ALSC	获取价格	Low Frequency EMI Reduction
ASM3P2531A-08SR	PULSECORE	获取价格	Clock Generator, 55MHz, CMOS, PDSO8, 0.150 INCH, SOIC-8
ASM3P2531A-08ST	ALSC	获取价格	Low Frequency EMI Reduction
ASM3P2531A-08ST	PULSECORE	获取价格	Clock Generator, 55MHz, CMOS, PDSO8, 0.150 INCH, SOIC-8
ASM3P2531A-08TR	ALSC	获取价格	Low Frequency EMI Reduction
ASM3P2531A-08TR	PULSECORE	获取价格	Clock Generator, 55MHz, CMOS, PDSO8, 4.40 MM, TSSOP-8

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