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ASM3I2872A-06OR

更新时间： 2024-11-23 22:56:35

品牌	Logo	应用领域
ALSC		晶体时钟发生器微控制器和处理器外围集成电路光电二极管
页数	文件大小	规格书
12页	179K
描述
Low Power Peak EMI Reducing Solution

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中文翻译

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数据手册

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ASM3I2872A-06OR 数据手册

October 2005

rev 1.6

ASM3P2872A

Low Power Peak EMI Reducing Solution

Features

The ASM3P2872A uses the most efficient and optimized

modulation profile approved by the FCC and is

implemented by using a proprietary all digital method.

Generates an EMI optimized clock signal at the

output

Integrated loop filter components

Operates with a 3.3V / 2.5V supply

Operating current less than 6mA

Low power CMOS design

Input frequency range: 13MHz to 30MHz for 2.5V

: 13MHz to 30MHz for 3.3V

Generates a 1X low EMI spread spectrum clock of

the input frequency

Frequency deviation: -1.25% @ 30MHz

Available in 6-pin TSOT-23, 8-pin SOIC and 8-pin

TSSOP packages.

The ASM3P2872A modulates the output of a single PLL

in order to “spread” the bandwidth of a synthesized clock,

and more importantly, decreases the peak amplitudes of

its harmonics. This results in significantly lower system

EMI compared to the typical narrow band signal produced

by oscillators and most frequency generators. Lowering

EMI by increasing a signal’s bandwidth is called ‘spread

spectrum clock generation’.

Applications

The ASM3P2872A is targeted towards all portable

devices with very low power requirements like MP3

players, Notebooks and digital still cameras.

Product Description

The ASM3P2872A is

a versatile spread spectrum

frequency modulator designed specifically for a wide

range of clock frequencies. The ASM3P2872A reduces

electromagnetic interference (EMI) at the clock source,

allowing system wide reduction of EMI of all clock

dependent signals. The ASM3P2872A allows significant

system cost savings by reducing the number of circuit

board layers ferrite beads, shielding that are traditionally

required to pass EMI regulations.

Key Specifications

Description

Supply voltages

Cycle-to-Cycle Jitter

Output Duty Cycle

Modulation Rate Equation

Frequency Deviation

Specification

VDD = 3.3V /2.5V

200pS (Max)

45/55% (worst case)

F_IN/640

-1.25% @ 30MHz

Block Diagram

VDD

PLL

Modulation

XIN

Crystal

Frequency

Divider

XOUT

Oscillator

Output

Divider

Phase

Loop

Filter

VCO

Detector

Feedback

Divider

ModOUT

REFOUT

VSS

Alliance Semiconductor

2575 Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com

Notice: The information in this document is subject to change without notice.

12 3 4 5 6 7...12

中文翻译

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与ASM3I2872A-06OR相关器件

型号	品牌	获取价格	描述	数据表
ASM3I2872A-08SR	ALSC	获取价格	Low Power Peak EMI Reducing Solution
ASM3I2872A-08SR	PULSECORE	获取价格	Clock Generator, 30MHz, CMOS, PDSO8, SOIC-8
ASM3I2872A-08ST	ALSC	获取价格	Low Power Peak EMI Reducing Solution
ASM3I2872A-08TR	ALSC	获取价格	Low Power Peak EMI Reducing Solution
ASM3I2872A-08TT	ALSC	获取价格	Low Power Peak EMI Reducing Solution
ASM3I2872AF-06OR	ALSC	获取价格	Low Power Peak EMI Reducing Solution
ASM3I2872AF-06OR	PULSECORE	获取价格	Low Power Peak EMI Reducing Solution
ASM3I2872AF-08SR	PULSECORE	获取价格	Low Power Peak EMI Reducing Solution
ASM3I2872AF-08SR	ALSC	获取价格	Low Power Peak EMI Reducing Solution
ASM3I2872AF-08ST	ALSC	获取价格	Low Power Peak EMI Reducing Solution

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