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ASM3I2760A-08TT PDF预览

ASM3I2760A-08TT

更新时间: 2024-11-06 22:56:35
品牌 Logo 应用领域
ALSC 晶体时钟发生器微控制器和处理器外围集成电路光电二极管
页数 文件大小 规格书
12页 180K
描述
Low Power Peak EMI Reducing Solution

ASM3I2760A-08TT 数据手册

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September 2005  
rev 1.8  
ASM3P2760A  
Low Power Peak EMI Reducing Solution  
Features  
The ASM3P2760A uses the most efficient and optimized  
modulation profile approved by the FCC and is  
implemented by using a proprietary all digital method.  
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Generates an EMI optimized clock signal at the  
output.  
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Integrated loop filter components.  
Operates with a 3.3V / 2.5V Supply.  
Operating current less than 4mA.  
Low power CMOS design.  
Input frequency range: 6MHz to 12MHz for 2.5V.  
: 6MHz to 13MHz for 3.3V.  
Generates a 1X low EMI spread spectrum clock of  
the input frequency.  
Frequency deviation: ±0.65% @ 8MHz  
Available in 6 pin TSOT-23, 8 pin SOIC and  
8 pin TSSOP Packages.  
The ASM3P2760A modulates the output of a single PLL  
in order to “spread” the bandwidth of a synthesized clock,  
and more importantly, decreases the peak amplitudes of  
its harmonics. This results in significantly lower system  
EMI compared to the typical narrow band signal produced  
by oscillators and most frequency generators. Lowering  
EMI by increasing a signal’s bandwidth is called ‘spread  
spectrum clock generation’.  
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Applications  
The ASM3P2760A is targeted towards all portable  
devices with very low power requirements like MP3  
players and digital still cameras.  
Product Description  
The ASM3P2760A is  
a versatile spread spectrum  
frequency modulator designed specifically for a wide  
range of clock frequencies. The ASM3P2760A reduces  
electromagnetic interference (EMI) at the clock source,  
allowing system wide reduction of EMI of all clock  
dependent signals. The ASM3P2760A allows significant  
system cost savings by reducing the number of circuit  
board layers ferrite beads, shielding that are traditionally  
required to pass EMI regulations.  
Key Specifications  
Description  
Supply voltages  
Cycle-to-Cycle Jitter  
Output Duty Cycle  
Modulation Rate Equation  
Frequency Deviation  
Specification  
VDD = 3.3V / 2.5V  
200pS (Max)  
45/55%  
FIN/256  
±0.65% @ 8MHz  
Block Diagram  
VDD  
PD  
PLL  
Modulation  
XIN  
Crystal  
Frequency  
Divider  
Oscillator  
Output  
Divider  
Phase  
Loop  
XOUT  
VCO  
Detector  
Filter  
Feedback  
Divider  
ModOUT  
VSS  
Alliance Semiconductor  
2575 Augustine Drive Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com  
Notice: The information in this document is subject to change without notice.  

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