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ASM2P3805AHG-20-SR PDF预览

ASM2P3805AHG-20-SR

更新时间: 2024-11-06 22:05:31
品牌 Logo 应用领域
ALSC 时钟驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
13页 533K
描述
3.3V CMOS Buffer Clock Driver

ASM2P3805AHG-20-SR 数据手册

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June 2005  
rev 0.2  
ASM2P3805AH  
3.3V CMOS Buffer Clock Driver  
Functional Description  
Features  
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Advanced CMOS Technology  
The ASM2P3805AH is a 3.3V, non-inverting clock driver  
built using advanced CMOS technology. The device  
consists of two banks of drivers, each with a 1:5 fanout and  
its own output enable control. The device has a "heartbeat"  
monitor for diagnostics and PLL driving. The MON output is  
identical to all other outputs and complies with the output  
specifications in this document. The ASM2P3805AH offers  
low capacitance inputs.  
Guaranteed low skew < 500pS (max.)  
Very low duty cycle distortion < 1.0nS (max)  
Very low CMOS power levels  
TTL compatible inputs and outputs  
Inputs can be driven from 3.3V or 5V components  
Two independent output banks with 3-state control  
1:5 fanout per bank  
"Heartbeat" monitor output  
VCC = 3.3V ± 0.3V  
The ASM2P3805AH is designed for high speed clock  
distribution where signal quality and skew are critical. The  
Available in SSOP, SOIC and QSOP Packages  
ASM2P3805AH  
also  
allows  
single  
point-to-point  
transmission line driving in applications such as address  
distribution, where one signal must be distributed to  
multiple receivers with low skew and high signal quality.  
Block Diagram  
Pin Diagram  
VCCA  
VCCB  
OB1  
1
2
20  
19  
OA1  
OA2  
A
S
M
2
OEA  
INA  
OB2  
OB3  
GNDB  
OB4  
OB5  
MON  
OEB  
INB  
3
4
18  
17  
16  
15  
5
OA3  
OA1 – OA5  
GNDA  
OA4  
5
3
8
6
7
0
OA5  
5
14  
5
INB  
OB1 – OB5  
MON  
A
H
GNDQ  
OEA  
8
13  
12  
11  
OEB  
9
INA  
10  
Alliance Semiconductor  
2575, Augustine Drive Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com  
Notice: The information in this document is subject to change without notice.  

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