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ASM2P20807A-20-DR PDF预览

ASM2P20807A-20-DR

更新时间: 2024-10-02 22:06:47
品牌 Logo 应用领域
ALSC 时钟驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
11页 466K
描述
2.5V CMOS 1-TO-10 CLOCK DRIVER

ASM2P20807A-20-DR 数据手册

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June 2005  
rev 0.2  
ASM2P20807A  
2.5V CMOS 1-TO-10 CLOCK DRIVER  
Product Description  
Features  
• High frequency > 150MHz  
The ASM2P20807A is a 2.5V compatible, high speed, low  
noise, 1:10 fanout, non-inverting clock buffer. The large  
fanout from a single input reduces loading on the preceding  
driver and provides an efficient clock distribution network.  
• Guaranteed low skew < 150pS (max.) between any two  
outputs  
• Very low duty cycle distortion < 300pS  
• High speed: propagation delay < 3nS  
• Very low CMOS power levels  
• TTL compatible inputs and outputs  
• 1:10 fanout  
Providing output to output skew as low as 150pS, the  
ASM20807A is an ideal clock distribution device for  
synchronous systems. Multiple power and grounds reduce  
noise. Typical applications are clock and signal distribution.  
• Maximum output rise and fall time < 1.25nS (max.)  
• Low input capacitance: 3pF (typ)  
• 2.5V Supply Voltage  
• Available in SSOP and QSOP Packages  
Block Diagram  
O1  
O2  
O3  
O4  
O5  
IN  
O6  
O7  
O8  
O9  
O10  
Alliance Semiconductor  
2575, Augustine Drive Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com  
Notice: The information in this document is subject to change without notice.  

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