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ASM2I2310ANZ-28-AR PDF预览

ASM2I2310ANZ-28-AR

更新时间: 2024-02-24 12:21:06
品牌 Logo 应用领域
ALSC 逻辑集成电路光电二极管驱动动态存储器PC
页数 文件大小 规格书
12页 501K
描述
3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs

ASM2I2310ANZ-28-AR 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:0.209 INCH, SSOP-28Reach Compliance Code:unknown
风险等级:5.75Is Samacsys:N
系列:2310输入调节:STANDARD
JESD-30 代码:R-PDSO-G28JESD-609代码:e0
长度:10.2 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
功能数量:1反相输出次数:
端子数量:28实输出次数:10
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
传播延迟(tpd):3.5 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.225 ns座面最大高度:2 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:5.3 mmBase Number Matches:1

ASM2I2310ANZ-28-AR 数据手册

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June 2005  
rev 0.4  
ASM2I2310ANZ  
3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs  
Features  
Functional Description  
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One input to 10 output buffer/driver  
The ASM2I2310ANZ is a 3.3V buffer designed to distribute  
high-speed clocks in mobile PC applications. The part has  
10 outputs, 8 of which can be used to drive up to four  
SDRAM SO-DIMMs, and the remaining can be used for  
external feedback to a PLL. The device operates at 3.3V  
and outputs can run up to 133MHz, thus making it  
Supports up to four SDRAM SO-DIMMs  
Two additional outputs for feedback  
Serial interface for output control  
Low skew outputs  
Up to 133MHz operation  
Multiple VDD and VSS pins for noise reduction  
Dedicated OE pin for testing  
Space-saving 28 Pin SSOP package  
3.3V operation  
i
compatible with Pentium II® processors.  
The ASM2I2310ANZ also includes a serial interface (IIC),  
which can enable or disable each output clock. The IIC is  
Slave Receiver only and is Standard mode compliant. IIC  
Master can write into the IIC registers but cannot read  
back. The first two bytes after address should be ignored  
by IIC Block and data is valid after these two bytes as given  
in IIC Byte Flow Table. On power-up, all output clocks are  
enabled. A separate Output Enable pin facilitates testing on  
ATE.  
i Pentium II is a registered trademark of Intel Corporation  
Block Diagram  
BUF_IN  
SDRAM0  
SDRAM1  
SDRAM2  
SDRAM3  
SDRAM4  
SDATA  
Serial Interface  
Decoding  
SDRAM5  
SDRAM6  
SDRAM7  
SDRAM8  
SDRAM9  
SCLOCK  
OE  
Alliance Semiconductor  
2575, Augustine Drive Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com  
Notice: The information in this document is subject to change without notice.  

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