SHARC Processor
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
SUMMARY
KEY FEATURES—PROCESSOR CORE
High performance signal processor for communications,
graphics and imaging applications
40 MIPS, 25 ns instruction rate, single-cycle instruction
execution
Super Harvard Architecture
4 independent buses for dual data fetch, instruction fetch,
and nonintrusive I/O
120 MFLOPS peak, 80 MFLOPS sustained performance
Dual data address generators with modulo and bit-reverse
addressing)
32-bit IEEE floating-point computation units—multiplier,
ALU, and shifter
Efficient program sequencing with zero-overhead looping:
Single-cycle loop setup
Dual-ported on-chip SRAM and integrated I/O peripherals—a
complete system-on-a-chip
IEEE JTAG Standard 1149.1 Test Access Port and on-chip
emulation
Integrated multiprocessing features
240-lead thermally enhanced MQFP_PQ4 package, 225-ball
plastic ball grid array (PBGA), 240-lead hermetic CQFP
package
32-bit single-precision and 40-bit extended-precision IEEE
floating-point data formats or 32-bit fixed-point data
format
RoHS compliant packages
CORE PROCESSOR
DUAL-PORTED SRAM
INSTRUCTION
TIMER
JTAG
TWO INDEPENDENT
DUAL-PORTED BLOCKS
7
CACHE
TEST AND
EMULATION
32 ꢀ 48-BIT
PROCESSOR PORT
ADDR DATA
ADDR
I/O PORT
ADDR
ADDR
DATA
DATA
DATA
DAG1
DAG2
PROGRAM
SEQUENCER
8 ꢀ 4 ꢀ 32 8 ꢀ 4 ꢀ 24
EXTERNAL
PORT
IOD
48
IOA
17
24
PM ADDRESS BUS
32
48
ADDR BUS
MUX
DM ADDRESS BUS
32
MULTIPROCESSOR
INTERFACE
48
40/32
PM DATA BUS
DM DATA BUS
BUS
CONNECT
(PX)
DATA BUS
MUX
HOST PORT
S
DATA
REGISTER
FILE
DMA
CONTROLLER
4
IOP
REGISTERS
(MEMORY
MAPPED)
6
SERIAL PORTS
(2)
BARREL
SHIFTER
16 ꢀ 40-BIT
6
MULT
ALU
CONTROL,
STATUS AND
DATA BUFFERS
36
LINK PORTS
(6)
I/O PROCESSOR
Figure 1. Functional Block Diagram
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. F
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