AS8C403625
AS8C401825
128K X 36, 256K X 18
3.3V Synchronous SRAMs
3.3V I/O, Flow-Through Outputs
Burst Counter, Single Cycle Deselect
Description
Features
◆
TheAS8C403625/1825 are high-speed SRAMs organized as
128Kx36/256Kx18.TheAS8C403625/1825SRAMs containwrite,data,
address andcontrolregisters.Therearenoregisters inthedataoutput
path(flow-througharchitecture).InternallogicallowstheSRAMtogen-
erateaself-timedwritebaseduponadecisionwhichcanbeleftuntilthe
endofthe write cycle.
128K x 36, 256K x 18 memory configurations
◆
Supports fast access times:
Commercial:
– 7.5ns up to 117MHz clock frequency
Theburstmodefeatureoffersthehighestlevelofperformancetothe
systemdesigner,astheAS8C403625/1825canprovidefourcyclesofdata
forasingleaddress presentedtotheSRAM. Aninternalburstaddress
counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe
accesssequence.Thefirstcycleofoutputdatawillflow-throughfromthe
arrayafteraclock-to-dataaccesstimedelayfromtherisingclockedgeof
the same cycle. If burst mode operation is selected (ADV=LOW), the
subsequentthreecyclesofoutputdatawillbeavailabletotheuseronthe
next three rising clock edges. The order of these three addresses are
definedbytheinternalburstcounterandtheLBO inputpin.
◆
LBO input selects interleaved or linear burst mode
Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite
enable (BWE), and byte writes (BWx)
3.3V core power supply
Power down controlled by ZZ input
3.3V I/O
Optional - Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
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Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack(TQFP),
The AS8C403625/1825 SRAMs utilize IDT’s latest high-performance
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm
100-pinthinplasticquadflatpack(TQFP)
PinDescriptionSummary
A0-A17
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Chip Enable
CE
CS
0
, CS
1
Chip Selects
Output Enable
OE
GW
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
BWE
BW , BW
1
2
, BW
3
, BW (1)
4
CLK
Clock
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
N/A
Synchronous
Synchronous
Synchronous
DC
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Linear / Interleaved Burst Order
Test Mode Select
Test Data Input
ADV
ADSC
ADSP
LBO
TMS
TDI
Synchronous
Synchronous
N/A
TCK
TDO
Test Clock
Test Data Output
Synchronous
Asynchronous
Asynchronous
Synchronous
N/A
JTAG Reset (Optional)
Sleep Mode
TRST
ZZ
I/O
0
-I/O31, I/OP1-I/OP4
DD, VDDQ
SS
Data Input / Output
Core Power, I/O Power
Ground
V
Supply
Supply
V
N/A
NOTE:
SEPTEMBER 522800tbl101 0
1. BW3 and BW4 are not applicable for the AS8C401825.
1
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DSC-5280/08
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