Data Sheet
AS8202NF
TTP-C2NF Communication Controller
ꢀ
40 MHz main clock with support for 10 MHz crystal,
10 MHz oscillator or 40 MHz oscillator
1 General Description
The AS8202NF communication controller is an
integrated device supporting serial communication
according to the TTP specification version 1.1. It
performs all communication tasks such as reception and
transmission of messages in a TTP cluster without
interaction of the host CPU. TTP provides mechanisms
that allow the deployment in high-dependability
distributed real-time systems. It provides the following
services:
ꢀ
16 MHz bus guardian clock with support for 16 MHz
crystal or 16 MHz oscillator
ꢀ
ꢀ
ꢀ
Single power supply 3.3V, 0.35µm CMOS process
Full automotive temperature range (-40ºC to 125ºC)
16k x 16 SRAM for message, status, control area
(communication network interface) and for
scheduling information (MEDL)
ꢀ
4k x 16 (plus parity) instruction code RAM for
protocol execution code
ꢀ Predictable transmission of messages with minimal
jitter
ꢀ
ꢀ
Data sheet conforms to protocol revision 2.04
ꢀ Fault-tolerant distributed clock synchronization
ꢀ Consistent membership service with small delay
ꢀ Masking of single faults
16k x 16 instruction code ROM containing startup
execution code and deprecated protocol code
revision 1.00
ꢀ
16 Bit non-multiplexed asynchronous host CPU
interface
2 Key Features
ꢀ Dual-channel controller for redundant data transfers
ꢀ
ꢀ
16 Bit RISC architecture
Software tools, design support, development boards
available (www.tttech.com)
ꢀ Dedicated controller supporting TTP (time-triggered
ꢀ
ꢀ
Certification support package according to RTCA/
DO-254 DAL A available (www.tttech.com)
protocol class C)
ꢀ Suited for dependable distributed real-time systems
80 pin LQFP80 Package
with guaranteed response time
ꢀ Asynchronous data rate up to 5 Mbit/s (MFM/
Manchester)
3 Applications
Application fields: automotive (by-wire braking, steering,
vehicle dynamics control, drive train control), aerospace
(aircraft electronic systems), industrial systems, railway
systems.
ꢀ Synchronous data rate 5 to 25 Mbit/s
ꢀ Bus interface (speed, encoding) for each channel
selectable independently
Figure 1. Block Diagram
D[15:0]
RxD[1:0]
RXCLK[1:0]
RxDV[1:0]
RXER[1:0]
Receiver
Host
Processor
Interface
A[11:0]
CEB
OEB
WEB
READYB
INTB
TTP Bus
Media
Drivers
TTP
Protocol
processor core
Communication
network
XIN1
XOUT1
Bus guardian
Transmitter
LED[2:0]
RAM_CLK_TESTSE
USE_RAM_CLK
interface
(CNI)
TxD[1:0]
CTS[1:0]
TxCLK[1:0]
AS8202NF
RAM_CLK_TESTSE
FTEST
Instruction
memory
RAM & ROM
Test
Test
Interface
XIN0
XOUT0
PLLOFF
STEST
Quartz or
Oscillator
Interface
FIDIS
TTEST
RESETB
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Revision 2.1
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