March 2001
AS7C513
AS7C3513
®
5V/3.3V 32K×16 CMOS SRAM
Features
• AS7C513 (5V version)
• AS7C3513 (3.3V version)
• Low power consumption: STANDBY
- 28 mW (AS7C513) / max CMOS
- 18 mW (AS7C3513) / max CMOS
• 2.0V data retention
• Easy memory expansion with CE, OE inputs
• TTL-compatible, three-state I/O
• 44-pin JEDEC standard package
- 400 mil SOJ
- 400 mil TSOP II
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
• Industrial and commercial temperature
• Organization: 32,768 words × 16 bits
• Center power and ground pins
• High speed
- 12/15/20 ns address access time
- 6,7,8 ns output enable access time
• Low power consumption: ACTIVE
- 800 mW (AS7C513) / max @ 12 ns
- 432 mW (AS7C3513) / max @ 12 ns
Logic block diagram
Pin arrangement
A0
A1
A2
44-Pin SOJ, TSOP II (400 mil)
V
CC
32K × 16
Array
GND
NC
A3
1
2
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A5
A3
A4
A5
A6
A7
A2
3
A6
A1
4
OE
A0
5
UB
CE
6
LB
I/O0
I/O1
I/O2
I/O3
7
8
9
I/O15
I/O14
I/O13
I/O12
GND
I/O0–I/O7
I/O
buffer
Control circuit
10
11
12
13
14
15
16
17
18
19
20
21
22
I/O8–I/O15
V
CC
GND
I/O4
I/O5
I/O6
I/O7
WE
A14
A13
A12
A11
NC
V
CC
Column decoder
I/O11
I/O10
I/O9
I/O8
NC
A7
A8
A9
A10
NC
WE
UB
OE
LB
CE
Selection guide
AS7C513-12
AS7C513-15
AS7C513-20
AS7C3513-12
AS7C3513-15
AS7C3513-20
Unit
ns
Maximum address access time
12
5
15
7
20
9
Maximum output enable access time
ns
AS7C513
AS7C3513
AS7C513
AS7C3513
160
120
5
150
110
5
140
100
5
mA
mA
mA
mA
Maximum operating current
Maximum CMOS standby current
5
5
5
Shaded areas indicate advance information.
3/23/01; v.1.0
Alliance Semiconductor
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