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AS7C4098A_06 PDF预览

AS7C4098A_06

更新时间: 2024-11-23 04:32:59
品牌 Logo 应用领域
ALSC 静态存储器
页数 文件大小 规格书
11页 258K
描述
5.0 V 256 K 】 16 CMOS SRAM

AS7C4098A_06 数据手册

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AS7C4098A  
February 2006  
®
5.0 V 256 K × 16 CMOS SRAM  
Features  
• Pin compatible with AS7C4098  
• Industrial and commercial temperature  
• Organization: 262,144 words × 16 bits  
• Center power and ground pins  
• High speed  
- 10/12/15/20 ns address access time  
- 5/6 ns output enable access time  
• Low power consumption: ACTIVE  
- 990mW/max @ 10 ns  
• Easy memory expansion with CE, OE inputs  
• TTL- and CMOS-compatible, three-state I/O  
• 44-pin JEDEC standard packages  
- 400-mil SOJ  
- TSOP 2  
• ESD protection 2000 volts  
• Latch-up current 200 mA  
• Low power consumption: STANDBY  
- 55mW/max CMOS  
• Individual byte read/write controls  
Logic block diagram  
Pin arrangement for SOJ and TSOP 2  
44-pin (400 mil) SOJ  
TSOP2  
A0  
A1  
A2  
V
CC  
A0  
A1  
A2  
A3  
A4  
CE  
1
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
A17  
1024 × 256 × 16  
A3  
GND  
2
A16  
A4  
3
A15  
Array  
(4,194,304)  
A6  
4
OE  
A7  
A8  
5
UB  
6
LB  
A12  
A13  
I/O16  
I/O15  
I/O14  
I/O13  
GND  
VCC  
I/O12  
I/O11  
I/O10  
I/O1  
7
I/O2  
I/O3  
I/O4  
8
9
I/O1–I/O8  
I/O9–I/O16  
I/O  
buffer  
Control circuit  
10  
11  
12  
13  
14  
15  
VCC  
GND  
I/O5  
I/O6  
I/O7  
Column decoder  
WE  
I/O8  
WE  
A5  
16  
17  
18  
19  
20  
21  
22  
29  
28  
27  
26  
I/O9  
NC  
A14  
A13  
A12  
A11  
A10  
UB  
OE  
LB  
CE  
A6  
A7  
25  
24  
23  
A8  
A9  
Selection guide  
–10  
10  
–12  
–15  
–20  
20  
Unit  
ns  
Maximum address access time  
12  
6
15  
6
Maximum output enable access time  
Maximum operating current  
5
6
ns  
180  
10  
160  
10  
140  
10  
120  
10  
mA  
mA  
Maximum CMOS standby current  
2/21/06, v 1.2  
Alliance Semiconductor  
P. 1 of 11  
Copyright © Alliance Semiconductor. All rights reserved.  

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