AS7C4096-20TC

更新时间： 2024-11-04 22:53:55

品牌	Logo	应用领域
ALSC		静态存储器
页数	文件大小	规格书
9页	247K
描述
5V/3.3V 512K X8 CMOS SRAM

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中文翻译

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数据手册

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AS7C4096-20TC 数据手册

January 2005

AS7C4096

AS7C34096

5V/3.3V 512K × 8 CMOS SRAM

Features

• AS7C4096 (5V version)

• Low power consumption: STANDBY

- 110 mW (AS7C4096) / max CMOS

- 72 mW (AS7C34096) / max CMOS

• Equal access and cycle times

• AS7C34096 (3.3V version)

• Industrial and commercial temperature

• Organization: 524,288 words × 8 bits

• Center power and ground pins

• High speed

- 10/12/15/20 ns address access time

- 5/6/7/8 ns output enable access time

• Low power consumption: ACTIVE

- 1375 mW (AS7C4096) / max @ 12 ns

- 576 mW (AS7C34096) / max @ 10 ns

• Easy memory expansion with CE

• TTL-compatible, three-state I/O

• JEDEC standard packages

- 400 mil 36-pin SOJ

, OE inputs

- 44-pin TSOP 2

• ESD protection ≥ 2000 volts

• Latch-up current ≥ 100 mA

Logic block diagram

Pin arrangements

V_CC

36-pin SOJ (400 mil)

44-pin TSOP 2

GND

Input buffer

A18

A17

A16

A15

I/O1

I/O8

A17

A16

A15

524,288 × 8

I/O1

I/O2

V_CC

I/O8

Array

(4,194,304)

I/O7

GND

V_CC

I/O1

I/O2

V_CC

I/O8

I/O7

GND

I/O3

I/O4

GND

I/O6

I/O5

A14

A13

A12

A11

A10

V_CC

GND

I/O3

I/O4

I/O6

I/O5

A14

A13

A12

A11

A10

Column decoder

Control

Circuit

Selection guide

–10

–12

–15

–20

Unit

Maximum address access time

Maximum outputenable access time

AS7C4096

AS7C34096

AS7C4096

AS7C34096

–

250

130

220

110

180

100

Maximum operating current

160

–

Maximum CMOS standby current

1/13/05; v.1.9

Alliance Semiconductor

P. 1 of 9

12 3 4 5 6 7...9

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