Datasheet > AS7C3513C

AS7C3513C

更新时间： 2024-02-20 05:23:21

品牌	Logo	应用领域
ALSC		静态存储器
页数	文件大小	规格书
9页	136K
描述
3.3 V 32K X 16 CMOS SRAM

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数据手册

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AS7C3513C 数据手册

September 2006

AS7C3513C

Advance Information

3.3 V 32K X 16 CMOS SRAM

Features

• Industrial (-40^oto 85^oC) temperature

• Organization: 32,768 words × 16 bits

• Center power and ground pins for low noise

• High speed

• JEDEC standard packaging

- 44-pin 400 mil SOJ

- 44-pin TSOP 2

• ESD protection ≥ 2000 volts

- 10 ns address access time

- 5 ns output enable access time

• Low power consumption via chip deselect

• Upper and Lower byte pin

• Easy memory expansion with CE, OE inputs

• TTL-compatible, three-state I/O

Logic block diagram

Pin arrangement

44-Pin SOJ (400 mil), TSOP 2

V_CC

32,768 × 16

Array

GND

I/O15

I/O14

I/O13

I/O12

GND

V_CC

I/O11

I/O10

I/O9

I/O8

A10

I/O0

I/O1

I/O2

I/O3

V_CC

GND

I/O4

I/O5

I/O6

I/O7

A14

A13

A12

A11

I/O0–I/O7

I/O8–I/O15

I/O

buffer

Control circuit

Address decoder

9/5/06, v 1.0

Alliance Memory

P. 1 of 9

12 3 4 5 6 7...9

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