Datasheet > 存储 > SRAM> AS7C3513B-10JIN

AS7C3513B-10JIN

更新时间： 2024-01-21 21:50:09

品牌	Logo	应用领域
ALSC		存储内存集成电路静态存储器光电二极管
页数	文件大小	规格书
10页	218K
描述
3.3V 32K x 16 CMOS SRAM

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数据手册

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AS7C3513B-10JIN 数据手册

March 2004

AS7C3513B

3.3V 32K×16 CMOS SRAM

Features

• Industrial and commercial temperature

• Organization: 32,768 words × 16 bits

• Center power and ground pins

• High speed

• Easy memory expansion with CE, OE inputs

• TTL-compatible, three-state I/O

• 44-pin JEDEC standard package

• 400 mil SOJ

• 10/12/15/20 ns address access time

• 5, 6, 7, 8 ns output enable access time

• Low power consumption: ACTIVE

• 288 mW / max @ 10 ns

• 400 mil TSOP 2

• ESD protection > 2000 volts

• Latch-up current > 200 mA

• Low power consumption: STANDBY

• 18 mW / max CMOS

• 6T 0.18m CMOS Technology

Logic block diagram

Pin arrangement

44-Pin SOJ, TSOP 2 (400 mil)

32K × 16

Array

GND

I/O0

I/O15

I/O14

I/O13

I/O12

GND

I/O1

I/O2

I/O3

I/O0–I/O7

I/O8–I/O15

I/O

buffer

Control circuit

GND

I/O4

I/O5

I/O6

I/O7

A14

A13

A12

A11

Column decoder

I/O11

I/O10

I/O9

I/O8

A10

Selection guide

-10

-12

-15

-20

Unit

Maximum address access time

Maximum output enable access time

Maximum operating current

Maximum CMOS standby current

3/24/04, v.1.2

Alliance Semiconductor

P. 1 of 10

12 3 4 5 6 7...10

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