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AS7C3512-12JC PDF预览

AS7C3512-12JC

更新时间: 2024-11-09 20:26:39
品牌 Logo 应用领域
ALSC 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
8页 285K
描述
Standard SRAM, 64KX8, 12ns, CMOS, PDSO32, 0.300 INCH, PLASTIC, SOJ-32

AS7C3512-12JC 数据手册

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High Performance  
64K×8 3.3V  
AS7C3512  
AS7C3512L  
CMOS SRAM  
®
Low voltage 64K×8 CMOS SRAM  
Preliminary information  
Features  
• Equal access and cycle times  
• Organization: 65,536 words × 8 bits  
• Single 3.3 ±0.3V power supply  
• 5V tolerant I/O specification  
• High speed  
- 12/15/20/25/35 ns address access time  
- 3/4/5/6/8 ns output enable access time  
• Very low power consumption  
- Active: 250 mW max, 12 ns cycle  
- Standby:9.0 mW max, CMOS I/O  
1.8 mW max, CMOS I/O, L version  
• 2.0V data retention  
• Easy memory expansion with CE1, CE2 and OE inputs  
• TTL-compatible, three-state I/O  
• Ideal for cache and portable computing  
- 75% power reduction during CPU idle mode  
• 32-pin JEDEC standard packages  
- 300 mil PDIP and SOJ  
• ESD protection >2000 volts  
• Latch-up current >200 mA  
Logic block diagram  
Pin arrangement  
DIP, SOJ  
Vcc  
GND  
NC  
NC  
A14  
A12  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
1
2
3
4
5
6
7
8
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
Vcc  
A15  
CE2  
WE  
A13  
A8  
A9  
A11  
OE  
A10  
CE1  
I/O7  
I/O6  
I/O5  
I/O4  
I/O3  
Input buffer  
A0  
A1  
I/O7  
I/O0  
A2  
A3  
A4  
A5  
A6  
A7  
256×256×8  
Array  
9
10  
11  
12  
13  
14  
15  
16  
(524,288)  
A0  
I/O0  
I/O1  
I/O2  
GND  
WE  
OE  
Column decoder  
Control  
circuit  
CE1  
CE2  
A
8
A A A A A A A  
9 10 11 12 13 14 15  
Selection guide  
7C3512-12 7C3512-15 7C3512-20 7C3512-25 7C3512-35 Unit  
Maximum address access time  
Maximum output enable access time  
Maximum operating current  
12  
3
15  
4
20  
5
25  
6
35  
8
ns  
ns  
70  
2.5  
0.5  
65  
2.5  
0.5  
60  
2.5  
0.5  
55  
2.5  
0.5  
50  
2.5  
0.5  
mA  
mA  
mA  
Maximum CMOS standby current  
L
Shaded areas contain advance information.  
ALLIANCE SEMICONDUCTOR  

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