Datasheet > 存储 > SRAM> AS7C34098A-15TI

AS7C34098A-15TI

更新时间： 2024-11-23 22:56:35

品牌	Logo	应用领域
ALSC		内存集成电路静态存储器光电二极管
页数	文件大小	规格书
10页	152K
描述
3.3 V 256 K x 16 CMOS SRAM

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数据手册

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AS7C34098A-15TI 数据手册

AS7C34098A

August 2004

3.3 V 256 K × 16 CMOS SRAM

Features

• Pin compatible with AS7C34098

• Industrial and commercial temperature

• Organization: 262,144 words × 16 bits

• Center power and ground pins

• High speed

- 10/12/15/20 ns address access time

- 4/5/6/7 ns output enable access time

• Low power consumption: ACTIVE

- 650 mW /max @ 10 ns

• Easy memory expansion with CE, OE inputs

• TTL- and CMOS-compatible, three-state I/O

• 44-pin JEDEC standard packages

- 400-mil SOJ

- TSOP 2

• ESD protection ≥ 2000 volts

• Latch-up current ≥ 200 mA

• Low power consumption: STANDBY

- 28.8 mW /max CMOS

• Individual byte read/write controls

Logic block diagram

Pin arrangement for SOJ and TSOP 2

44-pin (400 mil) SOJ

TSOP2

A17

1024 × 256 × 16

GND

A16

A15

Array

(4,194,304)

A12

A13

I/O16

I/O15

I/O14

I/O13

GND

V_CC

I/O12

I/O11

I/O10

I/O1

I/O2

I/O3

I/O4

I/O1–I/O8

I/O9–I/O16

I/O

buffer

Control circuit

V_CC

GND

I/O5

I/O6

I/O7

Column decoder

I/O8

I/O9

A14

A13

A12

A11

A10

Selection guide

–10

–12

–15

–20

Unit

Maximum address access time

Maximum output enable access time

Industrial

180

170

160

150

140

130

110

100

Maximum operating current

Commercial

Maximum CMOS standby current

8/17/04, v. 2.1

Alliance Semiconductor

P. 1 of 10

12 3 4 5 6 7...10

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