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AS7C33512PFS32A-225BI PDF预览

AS7C33512PFS32A-225BI

更新时间: 2024-11-27 14:40:55
品牌 Logo 应用领域
ALSC 静态存储器内存集成电路
页数 文件大小 规格书
21页 463K
描述
Standard SRAM, 512KX32, 6.9ns, CMOS, PBGA165, BGA-165

AS7C33512PFS32A-225BI 数据手册

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December 2002  
Advance Information  
AS7C33512PFS32A  
AS7C33512PFS36A  
®
3.3V 512K × 32/ 36 pipelined burst synchronous SRAM  
Features  
• 3.3V core power supply  
• Organization: 524,288 words × 32 or 36 bits  
Fast clock speeds to 250MHz in LVTTL/ LVCMOS  
Fast clock to data access: 2.6/ 2.8/ 3/ 3.4 ns  
Fast OEaccess time: 2.6/ 2.8/ 3/ 3.4 ns  
Fully synchronous register-to-register operation  
Single register flow-through mode  
• 2.5V or 3.3V I/ O operation with separate VDDQ  
Linear or interleaved burst control  
Snooze mode for reduced power-standby  
Common data inputs and data outputs  
Boundary scan using IEEE 1149.1 JTAG function  
• NTD™1 pipelined architecture available  
(AS7C331MNTD18A, AS7C33512NTD32A/  
AS7C33512NTD36A)  
Single-cycle deselect  
- Dual-cycle deselect also available (AS7C331MPFD18A,  
AS7C33512PFD32A/ AS7C33512PFD36A)  
Asynchronous output enable control  
Available in 100-pin TQFP package and 165-ball BGA  
• Individual byte write and global write  
• Multiple chip enables for easy expansion  
1 NTD™ is a trademark of Alliance Semiconductor Corporation. All trademarks  
mentioned in this document are the property of their respective owners.  
Logic block diagram  
LBO  
CLK  
ADV  
CLK  
CE  
CLR  
Burst logic  
ADSC  
ADSP  
512K × 32/ 36  
Memory  
19  
17  
19  
19  
array  
D
CE  
CLK  
Q
A[18:0]  
Address  
register  
36/ 32  
36/ 32  
GWE  
BWE  
D
Q
Q
Q
Q
DQd  
Byte write  
registers  
BW  
d
CLK  
D
DQc  
BW  
c
Byte write  
registers  
CLK  
D
DQb  
BW  
b
Byte write  
registers  
CLK  
D
DQa  
4
BW  
a
Byte write  
registers  
CLK  
CE0  
CE1  
CE2  
OE  
Output  
registers  
CLK  
D
Q
Input  
registers  
CLK  
Enable  
register  
CE  
CLK  
D
Q
Enable  
delay  
Power  
down  
ZZ  
register  
CLK  
36/ 32  
DQ[a:d]  
OE  
FT  
Selection guide  
-250  
4
-225  
4.4  
-200  
5
-166  
6
Units  
ns  
Minimum cycle time  
Maximum clock frequency  
250  
2.6  
450  
160  
70  
225  
2.8  
200  
3.0  
400  
130  
70  
166  
3.4  
350  
120  
70  
MHz  
ns  
Maximum pipelined clock access time  
Maximum operating current  
425  
150  
70  
mA  
mA  
mA  
Maximum standby current  
Maximum CMOS standby current (DC)  
12/ 2/ 02, v. 0.9.8 Advance Info  
Alliance Semiconductor  
1 of 21  
Copyright © Alliance Semiconductor. All rights reserved.  

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