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AS7C33512PFD18A-133TQC PDF预览

AS7C33512PFD18A-133TQC

更新时间: 2024-11-23 22:26:39
品牌 Logo 应用领域
ALSC 静态存储器
页数 文件大小 规格书
20页 516K
描述
3.3V 512K x 18 pipeline burst synchronous SRAM

AS7C33512PFD18A-133TQC 数据手册

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November 2004  
AS7C33512PFD18A  
®
3.3V 512K × 18 pipeline burst synchronous SRAM  
Features  
• Linear or interleaved burst control  
• Organization: 524,288 words × 18 bits  
• Fast clock speeds to 166 MHz  
• Fast clock to data access: 3.5/4.0 ns  
• Fast OE access time: 3.5/4.0 ns  
• Fully synchronous register-to-register operation  
• Dual-cycle deselect  
• Asynchronous output enable control  
• Individual byte write and global write  
• Available in 100-pin TQFP package  
• Snooze mode for reduced power-standby  
• Common data inputs and data outputs  
• Byte write enables  
• Multiple chip enables for easy expansion  
• 3.3V core power supply  
• 2.5V or 3.3V I/O operation with separate V  
DDQ  
Logic block diagram  
LBO  
Burst logic  
CLK  
ADV  
CLK  
CS  
CLR  
ADSC  
ADSP  
512K × 18  
Memory  
array  
19 17  
19  
19  
Q
D
A[18:0]  
Address  
register  
CS  
CLK  
18  
18  
2
GWE  
BWb  
D
Q
DQb  
Byte Write  
registers  
BWE  
BWa  
CLK  
D
Q
DQa  
Byte Write  
registers  
CLK  
CE0  
CE1  
OE  
Output  
D
Q
Q
Input  
registers  
Enable  
register  
CE  
CLK  
CE2  
registers  
CLK  
CLK  
D
Enable  
delay  
register  
CLK  
Power  
down  
ZZ  
OE  
18  
DQ[a,b]  
Selection guide  
–166  
6
–133  
7.5  
133  
4
Units  
Minimum cycle time  
ns  
MHz  
ns  
Maximum clock frequency  
Maximum clock access time  
Maximum operating current  
Maximum standby current  
Maximum CMOS standby current (DC)  
166  
3.5  
475  
130  
30  
425  
100  
30  
mA  
mA  
mA  
12/1/04; v.1.3  
Alliance Semiconductor  
1 of 20  
Copyright © Alliance Semiconductor. All rights reserved.  

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