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AS7C33512NTD36A-133TQC PDF预览

AS7C33512NTD36A-133TQC

更新时间: 2024-11-23 23:00:35
品牌 Logo 应用领域
ALSC 静态存储器
页数 文件大小 规格书
18页 426K
描述
3.3V 512K x 32/36 Pipelined SRAM with NTD

AS7C33512NTD36A-133TQC 数据手册

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April 2005  
AS7C33512NTD32A  
AS7C33512NTD36A  
®
3.3V 512K × 32/36 Pipelined SRAM with NTDTM  
Features  
• Clock enable for operation hold  
• Multiple chip enables for easy expansion  
• 3.3V core power supply  
• 2.5V or 3.3V I/O operation with separate V  
• Self-timed write cycles  
• Organization: 524,288 words × 32 or 36 bits  
• NTD architecture for efficient bus operation  
• Fast clock speeds to 166 MHz  
DDQ  
• Fast clock to data access: 3.4/3.8 ns  
• Fast OE access time: 3.4/3.8 ns  
• Fully synchronous operation  
• Asynchronous output enable control  
• Available in 100-pin TQFP packages  
• Individual byte write and global write  
• Interleaved or linear burst modes  
• Snooze mode for standby operation  
Logic block diagram  
19  
19  
A[18:0]  
Q
D
Address  
register  
Burst logic  
CLK  
D
Q
CE0  
CE1  
CE2  
Write delay  
addr. registers  
CLK  
19  
R/W  
BWa  
Control  
logic  
CLK  
BWb  
BWc  
BWd  
ADV / LD  
LBO  
512K x 32/36  
SRAM  
ZZ  
CLK  
Array  
32/36  
32/36  
DQ[a,b,c,d]  
Data  
Input  
Register  
D
Q
32/36  
32/36  
CLK  
32/36  
CLK  
CEN  
CLK  
Output  
Register  
OE  
32/36  
OE  
DQ[a,b,c,d]  
Selection guide  
-166  
6
-133  
7.5  
133  
3.8  
275  
80  
Units  
ns  
Minimum cycle time  
Maximum clock frequency  
Maximum clock access time  
Maximum operating current  
Maximum standby current  
166  
3.4  
300  
90  
MHz  
ns  
mA  
mA  
mA  
Maximum CMOS standby current (DC)  
60  
60  
4/21/05, v 2.8  
Alliance Semiconductor  
P. 1 of 18  
Copyright © Alliance Semiconductor. All rights reserved.  

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