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AS7C33512NTD36A-133TQCN PDF预览

AS7C33512NTD36A-133TQCN

更新时间: 2024-11-27 20:18:15
品牌 Logo 应用领域
美国芯成 - ISSI 时钟静态存储器内存集成电路
页数 文件大小 规格书
18页 425K
描述
ZBT SRAM, 512KX36, 3.8ns, CMOS, PQFP100, 14 X 20 MM, LEAD FREE, TQFP-100

AS7C33512NTD36A-133TQCN 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP,针数:100
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.52
Is Samacsys:N最长访问时间:3.8 ns
其他特性:PIPELINED ARCHITECTUREJESD-30 代码:R-PQFP-G100
JESD-609代码:e3长度:20 mm
内存密度:18874368 bit内存集成电路类型:ZBT SRAM
内存宽度:36功能数量:1
端子数量:100字数:524288 words
字数代码:512000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:512KX36封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):245认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:14 mmBase Number Matches:1

AS7C33512NTD36A-133TQCN 数据手册

 浏览型号AS7C33512NTD36A-133TQCN的Datasheet PDF文件第2页浏览型号AS7C33512NTD36A-133TQCN的Datasheet PDF文件第3页浏览型号AS7C33512NTD36A-133TQCN的Datasheet PDF文件第4页浏览型号AS7C33512NTD36A-133TQCN的Datasheet PDF文件第5页浏览型号AS7C33512NTD36A-133TQCN的Datasheet PDF文件第6页浏览型号AS7C33512NTD36A-133TQCN的Datasheet PDF文件第7页 
April 2005  
AS7C33512NTD32A  
AS7C33512NTD36A  
®
3.3V 512K × 32/36 Pipelined SRAM with NTDTM  
Features  
• Clock enable for operation hold  
• Multiple chip enables for easy expansion  
• 3.3V core power supply  
• 2.5V or 3.3V I/O operation with separate V  
• Self-timed write cycles  
• Organization: 524,288 words × 32 or 36 bits  
• NTD architecture for efficient bus operation  
• Fast clock speeds to 166 MHz  
DDQ  
• Fast clock to data access: 3.4/3.8 ns  
• Fast OE access time: 3.4/3.8 ns  
• Fully synchronous operation  
• Asynchronous output enable control  
• Available in 100-pin TQFP packages  
• Individual byte write and global write  
• Interleaved or linear burst modes  
• Snooze mode for standby operation  
Logic block diagram  
19  
19  
A[18:0]  
Q
D
Address  
register  
Burst logic  
CLK  
D
Q
CE0  
CE1  
CE2  
Write delay  
addr. registers  
CLK  
19  
R/W  
BWa  
Control  
logic  
CLK  
BWb  
BWc  
BWd  
ADV / LD  
LBO  
512K x 32/36  
SRAM  
ZZ  
CLK  
Array  
32/36  
32/36  
DQ[a,b,c,d]  
Data  
Input  
Register  
D
Q
32/36  
32/36  
CLK  
32/36  
CLK  
CEN  
CLK  
Output  
Register  
OE  
32/36  
OE  
DQ[a,b,c,d]  
Selection guide  
-166  
6
-133  
7.5  
133  
3.8  
275  
80  
Units  
ns  
Minimum cycle time  
Maximum clock frequency  
Maximum clock access time  
Maximum operating current  
Maximum standby current  
166  
3.4  
300  
90  
MHz  
ns  
mA  
mA  
mA  
Maximum CMOS standby current (DC)  
60  
60  
4/21/05, v 2.8  
Alliance Semiconductor  
P. 1 of 18  
Copyright © Alliance Semiconductor. All rights reserved.  

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