Datasheet > AS7C33256PFS18B

AS7C33256PFS18B

更新时间： 2022-12-14 03:42:49

品牌	Logo	应用领域
ALSC		静态存储器
页数	文件大小	规格书
19页	536K
描述
3.3V 256K X 18 pipeline burst synchronous SRAM

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AS7C33256PFS18B 数据手册

AS7C33256PFS18B

December 2004

3.3V 256K × 18 pipeline burst synchronous SRAM

Features

• Individual byte write and global write

• Multiple chip enables for easy expansion

• Linear or interleaved burst control

• Snooze mode for reduced power-standby

• Common data inputs and data outputs

• 3.3V core power supply

• Organization: 262,144 words × 18 bits

• Fast clock speeds to 200 MHz

• Fast clock to data access: 3.0/3.5/4.0 ns

• Fast OE access time: 3.0/3.5/4.0 ns

• Fully synchronous register-to-register operation

• Single-cycle deselect

• 2.5V or 3.3V I/O operation with separate V

DDQ

• Asynchronous output enable control

• Available in 100-pin TQFP package

Logic block diagram

LBO

CLK

ADV

CLK

Burst logic

256K × 18

Memory

array

ADSC

ADSP

CLR

A[17:0]

Address

CLK

GWE

DQb

Byte Write

registers

CLK

BWE

DQa

Byte Write

registers

CLK

CE0

CE1

Output

registers

Input

registers

Enable

CE2

CLK

Enable

delay

Power

down

CLK

DQ [a,b]

Selection guide

–200

–166

–133

7.5

133

Units

Minimum cycle time

MHz

Maximum clock frequency

Maximum clock access time

Maximum operating current

Maximum standby current

200

3.0

375

130

166

3.5

350

100

325

Maximum CMOS standby current (DC)

12/10/04; v.1.7

Alliance Semiconductor

P. 1 of 19

12 3 4 5 6 7...19

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AS7C33256PFS18B-133TQC	ALSC	3.3V 256K X 18 pipeline burst synchronous SRAM	获取价格
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