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AS7C33256PFD36A-100BI PDF预览

AS7C33256PFD36A-100BI

更新时间: 2022-12-01 20:51:00
品牌 Logo 应用领域
ALSC 静态存储器
页数 文件大小 规格书
14页 584K
描述
Standard SRAM, 256KX36, 12ns, CMOS, PBGA119, 14 X 20 MM, BGA-119

AS7C33256PFD36A-100BI 数据手册

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April 2002  
Preliminary  
AS7C33256PFD32A  
AS7C33256PFD36A  
®
3.3V 256K × 32/36 pipeline burst synchronous SRAM  
Features  
• Organization: 262,144 words × 32 or 36 bits  
• Fast clock speeds to 166 MHz in LVTTL/LVCMOS  
• Fast clock to data access: 3.5/3.8/4.0/5.0 ns  
• Fast OE access time: 3.5/3.8/4.0/5.0 ns  
• Fully synchronous register-to-register operation  
• Single register “Flow-through” option  
• Asynchronous output enable control  
• Available in 100-pin TQFP and 119-pin BGA packages  
• Byte write enables  
• 3.3V core power supply  
• 2.5V or 3.3V I/O operation with separate V  
DDQ  
• 30 mW typical standby power in power down mode  
1
• Dual-cycle deselect  
• NTD™ pipeline architecture available  
- Single-cycle deselect also available (AS7C33256PFS32A/  
AS7C33256PFS36A)  
(AS7C33256NTD32A/ AS7C33256NTD36A)  
*
®
1
Pentium is a registered trademark of Intel Corporation. NTD™ is a  
trademark of Alliance Semiconductor Corporation. All trademarks  
mentioned in this document are the property of their respective owners  
• Available in both 2 chip enable and 3 chip enable  
- 2 CE part number is AS7C33256PFD32A2 or AS7C33256PFD36A2  
1
• Pentium® compatible architecture and timing  
Logic block diagram  
LBO  
CLK  
ADV  
ADSC  
ADSP  
CLK  
CE  
CLR  
Burst logic  
256K × 32/36  
Memory  
2
2
18  
array  
D
CE  
CLK  
Q
A[17:0]  
18  
16  
18  
Address  
register  
36/32  
36/32  
GWE  
D
Q
DQd  
BWE  
Byte write  
registers  
BW  
d
CLK  
D
Q
DQc  
Byte write  
registers  
BW  
c
CLK  
D
Q
DQb  
BW  
b
Byte write  
registers  
CLK  
D
Q
DQa  
Byte write  
registers  
4
BW  
a
CLK  
CE0  
CE1  
CE2  
OE  
Output  
registers  
CLK  
D
Q
Input  
registers  
CLK  
Enable  
register  
CE  
CLK  
D
Q
Enable  
delay  
Power  
down  
ZZ  
register  
CLK  
36/32  
OE  
FT  
DQ[a;d]  
Selection guide  
–166  
6
–150  
6.6  
–133  
–100  
10  
Units  
ns  
Minimum cycle time  
7.5  
133  
4
Maximum pipelined clock frequency  
Maximum pipelined clock access time  
Maximum operating current  
166  
3.5  
475  
130  
30  
150  
3.8  
100  
5
MHz  
ns  
450  
110  
30  
425  
100  
30  
325  
90  
mA  
mA  
mA  
Maximum standby current  
Maximum CMOS standby current (DC)  
4/15/02; v.1.8  
30  
Alliance Semiconductor  
P. 1 of 14  
Copyright © Alliance Semiconductor. All rights reserved.  

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