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AS7C33256NTF36A-75TQC PDF预览

AS7C33256NTF36A-75TQC

更新时间: 2024-11-30 23:00:31
品牌 Logo 应用领域
ALSC 静态存储器
页数 文件大小 规格书
18页 428K
描述
3.3V 256K x 2/36 Flowthrough Synchronous SRAM with NTD

AS7C33256NTF36A-75TQC 数据手册

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AS7C33256NTF32A  
AS7C33256NTF36A  
November 2004  
®
3.3V 256K×32/36 Flowthrough Synchronous SRAM with NTDTM  
Features  
• Organization: 262,144 words × 32 or 36 bits  
• NTDarchitecture for efficient bus operation  
• Fast clock to data access: 7.5/8.5/10 ns  
• Fast OE access time: 3.5/4.0 ns  
• Fully synchronous operation  
• 3.3 core power supply  
• 2.5V or 3.3V I/O operation with separate VDDQ  
• 30 mW typical standby power  
• Self-timed write cycles  
• Interleaved or linear burst modes  
• Snooze mode for standby operation  
• Flow-through mode  
• Asynchronous output enable control  
• Available in 100-pin TQFP  
• Byte write enables  
• Clock enable for operation hold  
• Multiple chip enables for easy expansion  
Logic Block Diagram  
18  
18  
Q
A[17:0]  
D
Address  
register  
Burst logic  
CLK  
D
Q
CE0  
CE1  
CE2  
Write delay  
addr. registers  
CLK  
18  
R/W  
BWa  
Control  
logic  
CLK  
BWb  
BWc  
BWd  
ADV / LD  
LBO  
256K x 32/36  
SRAM  
ZZ  
CLK  
Array  
32/36  
32/36  
DQ[a,b,c,d]  
Data  
Input  
Register  
D
Q
32/36  
32/36  
CLK  
32/36  
CLK  
CEN  
Output  
Buffer  
OE  
32/36  
OE  
DQ[a,b,c,d]  
Selection Guide  
-75  
8.5  
7.5  
300  
120  
30  
-85  
10  
-10  
12  
Units  
ns  
Minimum cycle time  
Maximum clock access time  
Maximum operating current  
Maximum standby current  
8.5  
280  
110  
30  
10  
ns  
240  
100  
30  
mA  
mA  
mA  
Maximum CMOS standby current (DC)  
11/8/04, v. 1.1  
Alliance Semiconductor  
P. 1 of 18  
Copyright © Alliance Semiconductor. All rights reserved.  

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