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AS7C33256NTD18B-166TQIN PDF预览

AS7C33256NTD18B-166TQIN

更新时间: 2024-11-02 23:00:31
品牌 Logo 应用领域
ALSC 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
18页 442K
描述
3.3V 256K x 8 Pipelined SRAM with NTD

AS7C33256NTD18B-166TQIN 数据手册

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February 2005  
AS7C33256NTD18B  
®
®
3.3V 256K×18 Pipelined SRAM with NTDTM  
Features  
• Organization: 262,144 words × 18 bits  
• NTDarchitecture for efficient bus operation  
• Fast clock speeds to 200 MHz  
• Fast clock to data access: 3.0/3.5/4.0 ns  
• Fast OE access time: 3.0/3.5/4.0 ns  
• Fully synchronous operation  
• Multiple chip enables for easy expansion  
• 3.3V core power supply  
• 2.5V or 3.3V I/O operation with separate VDDQ  
• Self-timed write cycles  
• Interleaved or linear burst modes  
• Snooze mode for standby operation  
• Asynchronous output enable control  
• Available in 100-pin TQFP package  
• Byte write enables  
• Clock enable for operation hold  
Logic block diagram  
18  
18  
Q
D
A[17:0]  
Address  
register  
Burst logic  
CLK  
D
Q
CE0  
CE1  
CE2  
Write delay  
addr. registers  
CLK  
18  
R/  
W
BWa  
BWb  
ADV / LD  
CLK  
Control  
logic  
256K x 18  
LBO  
ZZ  
SRAM  
Array  
CLK  
18  
18  
DQ [a:b]  
Q
D
Data  
Input  
Register  
18  
18  
CLK  
18  
CLK  
CEN  
CLK  
Output  
Register  
OE  
18  
OE  
DQ [a:b]  
Selection Guide  
-200  
5
-166  
6
-133  
7.5  
133  
4
Units  
ns  
Minimum cycle time  
Maximum clock frequency  
Maximum clock access time  
Maximum operating current  
Maximum standby current  
Maximum CMOS standby current (DC)  
200  
3.0  
375  
135  
30  
166  
3.5  
350  
120  
30  
MHz  
ns  
325  
110  
30  
mA  
mA  
mA  
2/8/05; v.1.5  
Alliance Semiconductor  
P. 1 of 18  
Copyright © Alliance Semiconductor. All rights reserved.  

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