Datasheet > 存储 > SRAM> AS7C33256NTD18B-133TQCN

AS7C33256NTD18B-133TQCN

更新时间： 2024-11-28 23:00:31

品牌	Logo	应用领域
ALSC		存储内存集成电路静态存储器时钟
页数	文件大小	规格书
18页	442K
描述
3.3V 256K x 8 Pipelined SRAM with NTD

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AS7C33256NTD18B-133TQCN 数据手册

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February 2005

AS7C33256NTD18B

3.3V 256K×18 Pipelined SRAM with NTD^TM

Features

• Organization: 262,144 words × 18 bits

• NTD^™architecture for efficient bus operation

• Fast clock speeds to 200 MHz

• Fast clock to data access: 3.0/3.5/4.0 ns

• Fast OE access time: 3.0/3.5/4.0 ns

• Fully synchronous operation

• Multiple chip enables for easy expansion

• 3.3V core power supply

• 2.5V or 3.3V I/O operation with separate V_DDQ

• Self-timed write cycles

• Interleaved or linear burst modes

• Snooze mode for standby operation

• Asynchronous output enable control

• Available in 100-pin TQFP package

• Byte write enables

• Clock enable for operation hold

Logic block diagram

A[17:0]

Address

Burst logic

CLK

CE0

CE1

CE2

Write delay

addr. registers

CLK

BWa

BWb

ADV / LD

CLK

Control

logic

256K x 18

LBO

SRAM

Array

CLK

DQ [a:b]

Data

Input

CLK

CEN

CLK

Output

DQ [a:b]

Selection Guide

-200

-166

-133

7.5

133

Units

Minimum cycle time

Maximum clock frequency

Maximum clock access time

Maximum operating current

Maximum standby current

Maximum CMOS standby current (DC)

200

3.0

375

135

166

3.5

350

120

MHz

325

110

2/8/05; v.1.5

Alliance Semiconductor

P. 1 of 18

12 3 4 5 6 7...18

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