Datasheet > AS7C33256FT32A

AS7C33256FT32A

更新时间： 2024-11-02 23:00:31

品牌	Logo	应用领域
ALSC		静态存储器
页数	文件大小	规格书
19页	523K
描述
3.3V 256K x 32/36 Flow-through synchronous SRAM

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中文翻译

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数据手册

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AS7C33256FT32A 数据手册

November 2004

AS7C33256FT32A

AS7C33256FT36A

3.3V 256K × 32/36 Flow-through synchronous SRAM

Features

• Organization: 262,144 words × 32 or 36 bits

• Fast clock to data access: 7.5/8.5/10 ns

• Fast OE access time: 3.5/4.0/4.0 ns

• Fully synchronous flow-through operation

• Asynchronous output enable control

• Available in 100-pin TQFP package

• Individual byte write and global write

• Multiple chip enables for easy expansion

• 3.3V core power supply

• 2.5V or 3.3V I/O operation with separate VDDQ

• Linear or interleaved burst control

• Snooze mode for reduced power-standby

• Common data inputs and data outputs

Logic block diagram

LBO

CLK

ADV

ADSC

ADSP

CLK

Burst logic

CLR

256K × 32/36

Memory

array

CLK

A[17:0]

Address

32/36

GWE

BWE

BW_d

DQ_d

Byte write

registers

CLK

DQ_c

Byte write

registers

BW_c

BW_b

CLK

DQ_b

Byte write

registers

CLK

DQ_a

Byte write

registers

BW_a

CLK

CE0

CE1

Output

registers

CE2

Input

registers

CLK

Enable

CLK

Enable

Power

down

delay

CLK

32/36

DQ[a:d]

Selection guide

-75

8.5

7.5

300

110

-85

-10

Units

Minimum cycle time

8.5

275

100

Maximum clock access time

Maximum operating current

Maximum standby current

250

Maximum CMOS standby current (DC)

11/30/04, v 1.1

Alliance Semiconductor

1 of 19

12 3 4 5 6 7...19

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