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AS7C331MPFD32A-167BIN PDF预览

AS7C331MPFD32A-167BIN

更新时间: 2024-11-03 19:56:07
品牌 Logo 应用领域
ALSC ISM频段静态存储器内存集成电路
页数 文件大小 规格书
23页 580K
描述
Standard SRAM, 1MX32, 3.4ns, CMOS, PBGA165, LEAD FREE, BGA-165

AS7C331MPFD32A-167BIN 数据手册

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April 2004  
AS7C331MPFD32A  
AS7C331MPFD36A  
®
3.3V 1M × 32/36 pipelined burst synchronous SRAM  
Features  
• 2.5V or 3.3V I/O operation with separate V  
• Linear or interleaved burst control  
• Snooze mode for reduced power-standby  
• Common data inputs and data outputs  
• Organization: 1,048,576 words × 32 or 36 bits  
• Fast clock speeds to 200 MHz in LVTTL/LVCMOS  
• Fast clock to data access: 3.1/3.4/3.8 ns  
• Fast OE access time: 3.1/3.4/3.8 ns  
• Fully synchronous register-to-register operation  
• Dual-cycle deselect  
DDQ  
• Boundary scan using IEEE 1149.1 JTAG function  
1
• NTD™ pipelined architecture available  
(AS7C332MNTD18A, AS7C331MNTD32A/  
AS7C331MNTD36A)  
- Single-cycle deselect also available (AS7C332MPFS18A,  
AS7C331MPFS32A/ AS7C331MPFS36A)  
• Asynchronous output enable control  
• Available in 100-pin TQFP and 165-ball BGA packages  
• Byte write enables  
1 NTD™ is a trademark of Alliance Semiconductor Corporation. All  
trademarks mentioned in this document are the property of their  
respective owners.  
• Multiple chip enables for easy expansion  
• 3.3V core power supply  
Logic block diagram  
LBO  
CLK  
ADV  
ADSC  
ADSP  
CLK  
CE  
CLR  
Q0  
Burst logic  
1M × 32/36  
Q1  
Memory  
array  
2
2
D
CE  
CLK  
Q
A[19:0]  
Address  
20  
20  
18  
20  
register  
32/36  
32/36  
GWE  
BWE  
BWd  
D
Q
DQd  
Byte write  
registers  
CLK  
D
Q
DQc  
Byte write  
registers  
BWc  
BWb  
CLK  
D
Q
DQb  
Byte write  
registers  
CLK  
D
Q
DQa  
Byte write  
registers  
4
BWa  
CLK  
CE0  
CE1  
OE  
Output  
registers  
D
Q
Q
CE2  
Input  
registers  
CLK  
Enable  
register  
CE  
CLK  
CLK  
D
Enable  
Power  
down  
delay  
register  
CLK  
ZZ  
32/36  
DQ[a:d]  
OE  
Selection guide  
-200  
5
-167  
-133  
7.5  
Units  
ns  
Minimum cycle time  
6
Maximum clock frequency  
Maximum clock access time  
Maximum operating current  
Maximum standby current  
200  
3.1  
400  
120  
70  
167  
3.4  
350  
110  
70  
133  
3.8  
MHz  
ns  
325  
100  
70  
mA  
mA  
mA  
Maximum CMOS standby current (DC)  
4/26/04, v.1.0  
Alliance Semiconductor  
1 of 23  
Copyright © Alliance Semiconductor. All rights reserved.  

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