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AS7C331MPFD18A PDF预览

AS7C331MPFD18A

更新时间: 2024-11-02 22:26:39
品牌 Logo 应用领域
ALSC 静态存储器
页数 文件大小 规格书
19页 511K
描述
3.3V 1M x 18 pipelined burst synchronous SRAM

AS7C331MPFD18A 数据手册

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February 2005  
AS7C331MPFD18A  
®
3.3V 1M x 18 pipelined burst synchronous SRAM  
Features  
• Organization: 1,048,576 x18 bits  
• Fast clock speeds to 166MHz  
• Fast clock to data access: 3.4/3.8 ns  
• Fast OE access time: 3.4/3.8 ns  
• Fully synchronous register-to-register operation  
• Double-cycle deselect  
Individual byte write and global write  
• Multiple chip enables for easy expansion  
• 3.3 V core power supply  
• 2.5 V or 3.3V I/O operation with separate VDDQ  
• Linear or interleaved burst control  
• Common data inputs and data outputs  
• Snooze mode for reduced power-standby  
• Asynchronous output enable control  
• Available 100-pin TQFP package  
Logic block diagram  
LBO  
CLK  
ADV  
ADSC  
ADSP  
CLK  
CS  
CLR  
Burst logic  
1M x 18  
Memory  
array  
20 18  
20  
20  
Q
D
A[19:0]  
Address  
register  
CS  
CLK  
18  
18  
2
GWE  
BWb  
D
Q
DQb  
Byte Write  
registers  
BWE  
BWa  
CLK  
D
Q
DQa  
Byte Write  
registers  
CLK  
CE0  
CE1  
OE  
Output  
registers  
D
Q
Q
Input  
registers  
Enable  
register  
CE  
CLK  
CE2  
CLK  
CLK  
D
Enable  
delay  
register  
CLK  
Power  
down  
ZZ  
OE  
18  
DQ[a,b]  
Selection guide  
-166  
6
-133  
7.5  
133  
3.8  
270  
80  
Units  
ns  
Minimum cycle time  
Maximum clock frequency  
166  
3.4  
290  
90  
MHz  
ns  
Maximum clock access time  
Maximum operating current  
Maximum standby current  
mA  
mA  
mA  
Maximum CMOS standby current (DC)  
60  
60  
2/10/05, v. 1.3  
Alliance Semiconductor  
1 of 19  
Copyright © Alliance Semiconductor. All rights reserved.  

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