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AS7C331MPFD18A-166BIN PDF预览

AS7C331MPFD18A-166BIN

更新时间: 2024-11-03 20:49:15
品牌 Logo 应用领域
ALSC 时钟ISM频段静态存储器内存集成电路
页数 文件大小 规格书
24页 571K
描述
Standard SRAM, 1MX18, 3.4ns, CMOS, PBGA165, LEAD FREE, BGA-165

AS7C331MPFD18A-166BIN 数据手册

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April 2004  
AS7C331MPFD18A  
®
3.3V 1M x 18 pipelined burst synchronous SRAM  
Features  
• Organization: 1,048,576 x18 bits  
• Multiple chip enables for easy expansion  
• 3.3 V core power supply  
• 2.5 V or 3.3V I/O operation with separate VDDQ  
• Linear or interleaved burst control  
• Fast clock speeds to 166MHz in LVTTL/LVCMOS  
• Fast clock to data access: 3.4/3.8 ns  
• Fast OE access time: 3.4/3.8 ns  
• Fully synchronous register-to-register operation  
• Dual-cycle deselect  
• Snooze mode for reduced power-standby  
• Boundary scan using IEEE 1149.1 JTAG function  
• NTD™1 pipelined architecture available (AS7C331MNTD18A,  
AS7C33512NTD32A/ AS7C33512NTD36A)  
• Single-cycle deselect also available (AS7C331MPFS18A,  
AS7C33512PFS32A/ AS7C33512PFS36A)  
• Asynchronous output enable control  
• Available 100-pin TQFP and 165-ball BGA packages  
• Byte write enables  
1 NTD™ is a trademark of Alliance Semiconductor Corporation. All trademarks  
mentioned in this document are the property of their respective owners  
Logic block diagram  
LBO  
CLK  
CLK  
CS  
CLR  
ADV  
ADSC  
ADSP  
Burst logic  
20 18  
Address  
CS register  
1M x 18  
Memory  
array  
20  
20  
Q
D
A[19:0]  
CLK  
18  
18  
2
GWE  
BWb  
D
Q
BytDeQWb rite  
registers  
BWE  
BWa  
CLK  
D
Q
BytDeQWa rite  
registers  
CLK  
CE0  
CE1  
CE2  
OE  
Q
DEnable  
Input  
Output  
registers  
register  
registers  
CE  
CLK  
CLK  
CLK  
Q
DEnable  
Power  
down  
delay  
ZZ  
register  
CLK  
OE  
18  
DQ[a,b]  
Selection guide  
-166  
6
-133  
7.5  
133  
3.8  
270  
80  
Units  
ns  
Minimum cycle time  
Maximum clock frequency  
166  
3.4  
290  
90  
MHz  
ns  
Maximum clock access time  
Maximum operating current  
Maximum standby current  
mA  
mA  
mA  
Maximum CMOS standby current (DC)  
40  
40  
4/12/04, v 1.0  
Alliance Semiconductor  
1 of 24  
Copyright © Alliance Semiconductor. All rights reserved.  

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