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AS7C331MNTF32A PDF预览

AS7C331MNTF32A

更新时间: 2024-11-18 23:04:23
品牌 Logo 应用领域
ALSC 静态存储器
页数 文件大小 规格书
18页 417K
描述
3.3V 1M x 32/36 Flowthrough SRAM with NTD

AS7C331MNTF32A 数据手册

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December 2004  
AS7C331MNTF32A  
AS7C331MNTF36A  
®
3.3V 1M × 32/36 Flowthrough SRAM with NTDTM  
Features  
• Byte write enables  
• Clock enable for operation hold  
• Multiple chip enables for easy expansion  
• 3.3V core power supply  
• 2.5V or 3.3V I/O operation with separate V  
• Self-timed write cycles  
• Organization: 1,048,576 words × 32 or 36 bits  
• NTD architecture for efficient bus operation  
• Fast clock to data access: 7.5/8.5/10 ns  
• Fast OE access time: 3.5/4.0 ns  
• Fully synchronous operation  
• Flow-through mode  
• Asynchronous output enable control  
• Available in 100-pin TQFP package  
DDQ  
• Interleaved or linear burst modes  
• Snooze mode for standby operation  
Logic block diagram  
20  
20  
A[19:0]  
Q
D
Address  
register  
Burst logic  
CLK  
D
Q
CE0  
CE1  
CE2  
Write delay  
addr. registers  
CLK  
20  
R/W  
BWa  
Control  
logic  
CLK  
BWb  
BWc  
BWd  
ADV / LD  
LBO  
1M x 32/36  
SRAM  
ZZ  
CLK  
Array  
32/36  
32/36  
DQ[a,b,c,d]  
Data  
Input  
Register  
D
Q
32/36  
32/36  
CLK  
32/36  
CLK  
CEN  
Output  
Buffer  
OE  
32/36  
OE  
DQ[a,b,c,d]  
Selection guide  
-75  
8.5  
7.5  
325  
140  
90  
-85  
10  
-10  
12  
Units  
Minimum cycle time  
ns  
ns  
Maximum clock access time  
Maximum operating current  
Maximum standby current  
8.5  
300  
130  
90  
10  
275  
130  
90  
mA  
mA  
mA  
Maximum CMOS standby current (DC)  
12/23/04, v 1.2  
Alliance Semiconductor  
P. 1 of 18  
Copyright © Alliance Semiconductor. All rights reserved.  

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