Datasheet > AS7C331MNTF18A-85BIN

AS7C331MNTF18A-85BIN

更新时间： 2024-11-23 19:47:27

品牌	Logo	应用领域
ALSC		时钟 ISM频段静态存储器内存集成电路
页数	文件大小	规格书
22页	441K
描述
ZBT SRAM, 1MX18, 8.5ns, CMOS, PBGA165, LEAD FREE, BGA-165

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May 2004

AS7C331MNTF18A

3.3V 1M x 18 Flowthrough Synchronous SRAM with NTD^TM

Features

• Available in 100-pin TQFP and 165-ball BGA package

• Byte write enables

• Clock enable for operation hold

• Multiple chip enables for easy expansion

• 3.3V core power supply

• Organization: 1,048,576 words × 18 bits

™1

• NTD architecture for efficient bus operation

• Fast clock to data access: 8.5/10 ns

• Fast OE access time: 3.4/3.8 ns

• Fully synchronous operation

• Flow-through mode

• 2.5V or 3.3V I/O operation with separate V

• Self-timed write cycles

DDQ

• Interleaved or linear burst modes

• Snooze mode for standby operation

• Asynchronous output enable control

1. NTD^TMis a trademark of Alliance Semiconductor Corporation.

Logic block diagram

A[19:0]

Address

burst logic

CLK

CE0

CE1

CE2

Write delay

addr. registers

CLK

R/W

BWa

BWb

Control

logic

CLK

ADV / LD

1M x 18

SRAM

array

LBO

CLK

DQ [a,b]

Data

input

CLK

CEN

Output

buffer

DQ [a,b]

Selection guide

-85

-10

Units

Minimum cycle time

Maximum clock access time

Maximum operating current

Maximum standby current

8.5

250

230

Maximum CMOS standby current (DC)

5/13/04, v 1.0

Alliance Semiconductor

P. 1 of 22

12 3 4 5 6 7...22

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