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AS7C331MNTF18A-10TQCN PDF预览

AS7C331MNTF18A-10TQCN

更新时间: 2024-11-02 23:04:23
品牌 Logo 应用领域
ALSC 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
18页 424K
描述
3.3V 1M x 18 Flowthrough Synchronous SRAM with NTD

AS7C331MNTF18A-10TQCN 数据手册

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December 2004  
AS7C331MNTF18A  
®
3.3V 1M x 18 Flowthrough Synchronous SRAM with NTDTM  
Features  
• Individual byte write and global write  
• Clock enable for operation hold  
• Multiple chip enables for easy expansion  
• 3.3V core power supply  
• 2.5V or 3.3V I/O operation with separate V  
• Self-timed write cycles  
• Organization: 1,048,576 words × 18 bits  
• NTD architecture for efficient bus operation  
• Fast clock to data access: 7.5/8.5/10 ns  
• Fast OE access time: 3.5/4.0 ns  
• Fully synchronous operation  
DDQ  
• Interleaved or linear burst modes  
• Snooze mode for standby operation  
• Flow-through mode  
• Asynchronous output enable control  
• Available in 100-pin TQFP package  
Logic block diagram  
20  
20  
A[19:0]  
Q
D
Address  
register  
burst logic  
CLK  
D
Q
CE0  
CE1  
CE2  
Write delay  
addr. registers  
CLK  
20  
R/W  
BWa  
BWb  
Control  
logic  
CLK  
ADV / LD  
1M x 18  
LBO  
ZZ  
SRAM  
array  
CLK  
18  
18  
DQ [a,b]  
Data  
input  
register  
D
Q
18  
18  
CLK  
18  
CLK  
CEN  
Output  
buffer  
OE  
18  
OE  
DQ [a,b]  
Selection guide  
-75  
-85  
10  
-10  
12  
Units  
Minimum cycle time  
8.5  
7.5  
275  
90  
ns  
ns  
Maximum clock access time  
Maximum operating current  
Maximum standby current  
8.5  
250  
80  
10  
230  
80  
mA  
mA  
mA  
Maximum CMOS standby current (DC)  
60  
60  
60  
12/23/04, v 1.2  
Alliance Semiconductor  
P. 1 of 18  
Copyright © Alliance Semiconductor. All rights reserved.  

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