Datasheet > 存储 > SRAM> AS7C331MNTD36A-200TQC

AS7C331MNTD36A-200TQC

更新时间： 2024-11-02 23:04:23

品牌	Logo	应用领域
ALSC		存储内存集成电路静态存储器时钟
页数	文件大小	规格书
18页	441K
描述
3.3V 1M x 32/36 Pipelined SRAM with NTD

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AS7C331MNTD36A-200TQC 数据手册

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December 2004

AS7C331MNTD32A

AS7C331MNTD36A

3.3V 1M × 32/36 Pipelined SRAM with NTD^TM

Features

• Organization: 1,048,576 words × 32 or 36 bits

• NTD^™architecture for efficient bus operation

• Fast clock speeds to 200 MHz

• Clock enable for operation hold

• Multiple chip enables for easy expansion

• 3.3V core power supply

• Fast clock to data access: 3.2/3.5/3.8 ns

• Fast OE access time: 3.2/3.5/3.8 ns

• Fully synchronous operation

• Asynchronous output enable control

• Available in 100-pin TQFP packages

• Byte write enables

• 2.5V or 3.3V I/O operation with separate V_DDQ

• Self-timed write cycles

• Interleaved or linear burst modes

• Snooze mode for standby operation

Logic block diagram

A[19:0]

Address

Burst logic

CLK

CE0

CE1

CE2

Write delay

addr. registers

CLK

R/W

BWa

Control

logic

CLK

BWb

BWc

BWd

1M x 32/36

SRAM

ADV / LD

LBO

CLK

Array

32/36

DQ[a,b,c,d]

Data

Input

32/36

CLK

32/36

CLK

CEN

CLK

Output

32/36

DQ[a,b,c,d]

Selection guide

-200

-166

-133

7.5

Units

Minimum cycle time

Maximum clock frequency

Maximum clock access time

Maximum operating current

Maximum standby current

200

3.2

450

170

166

3.5

400

150

133

3.8

MHz

350

140

Maximum CMOS standby current (DC)

12/23/04, V 1.6

Alliance Semiconductor

P. 1 of 18

12 3 4 5 6 7...18

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