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AS7C331MNTD32A-133BCN PDF预览

AS7C331MNTD32A-133BCN

更新时间: 2024-11-02 20:05:55
品牌 Logo 应用领域
ALSC 时钟ISM频段静态存储器内存集成电路
页数 文件大小 规格书
26页 550K
描述
ZBT SRAM, 1MX32, 3.8ns, CMOS, PBGA165, LEAD FREE, BGA-165

AS7C331MNTD32A-133BCN 数据手册

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November 2004  
AS7C331MNTD32A  
AS7C331MNTD36A  
®
3.3V 1M × 32/36 Pipelined SRAM with NTDTM  
Features  
• Organization: 1,048,576 words × 32 or 36 bits  
• NTDarchitecture for efficient bus operation  
• Fast clock speeds to 200 MHz  
• Fast clock to data access: 3.2/3.5/3.8 ns  
• Fast OE access time: 3.2/3.5/3.8 ns  
• Fully synchronous operation  
• Multiple chip enables for easy expansion  
• 3.3V core power supply  
• 2.5V or 3.3V I/O operation with separate VDDQ  
• Self-timed write cycles  
• Interleaved or linear burst modes  
• Snooze mode for standby operation  
• Boundary Scan using IEEE 1149.1 JTAG function is  
• Asynchronous output enable control  
• Available in 100-pin TQFP and 165-ball BGA packages available in 165 Ball BGA Package only.  
• Byte write enables  
• Clock enable for operation hold  
Logic block diagram  
20  
20  
Q
A[19:0]  
D
Address  
register  
Burst logic  
CLK  
D
Q
CE0  
CE1  
CE2  
Write delay  
addr. registers  
20  
CLK  
R/W  
BWa  
Control  
logic  
CLK  
BWb  
BWc  
BWd  
1M x 32/36  
SRAM  
ADV / LD  
LBO  
ZZ  
CLK  
Array  
32/36  
32/36  
DQ[a,b,c,d]  
Data  
Input  
Register  
D
Q
32/36  
32/36  
CLK  
32/36  
CLK  
CEN  
CLK  
Output  
Register  
OE  
32/36  
OE  
DQ[a,b,c,d]  
Selection guide  
-200  
5
-166  
6
-133  
7.5  
Units  
ns  
Minimum cycle time  
Maximum clock frequency  
Maximum clock access time  
Maximum operating current  
Maximum standby current  
200  
3.2  
450  
170  
90  
166  
3.5  
400  
150  
90  
133  
3.8  
MHz  
ns  
350  
140  
90  
mA  
mA  
mA  
Maximum CMOS standby current (DC)  
11/25/04, V 1.5  
Alliance Semiconductor  
P. 1 of 26  
Copyright © Alliance Semiconductor. All rights reserved.  

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