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AS7C33128PFS16A-133TQC PDF预览

AS7C33128PFS16A-133TQC

更新时间: 2024-11-01 23:31:47
品牌 Logo 应用领域
其他 - ETC 内存集成电路静态存储器
页数 文件大小 规格书
12页 286K
描述
x16 Fast Synchronous SRAM

AS7C33128PFS16A-133TQC 数据手册

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January 2002  
AS7C33128PFS16A  
AS7C33128PFS18A  
®
3.3V 128K × 16/18 pipeline burst synchronous SRAM  
Features  
• Organization: 131,072words × 16 or 18 bits  
• Fast clock speeds to 200MHz in LVTTL/LVCMOS  
• Fast clock to data access: 3.0/3.1/3.5/4.0/5.0 ns  
• Fast OE access time: 3.0/3.1/3.5/4.0/5.0 ns  
• Fully synchronous register-to-register operation  
• “Flow-through” mode  
• Byte write enables  
• Multiple chip enables for easy expansion  
• 3.3V core power supply  
• 2.5V or 3.3V I/O operation with separate V  
• 30 mW typical standby power in power down mode  
DDQ  
®
• Single-cycle deselect  
• Pentium® compatible architecture and timing  
• Asynchronous output enable control  
• Economical 100-pin TQFP package  
1. Pentium is a registered trademark of Intel Corporation. NTD™  
1
is a trademark of Alliance Semiconductor Corporation. All trade-  
marks mentioned in this document are the property of their respec-  
tive owners.  
Logic block diagram  
Pin arrangement  
LBO  
CLK  
ADV  
CLK  
CS  
Burst logic  
17 15  
128K × 16/18  
Memory  
ADSC  
ADSP  
CLR  
A16  
NC  
NC  
V
SSQ  
NC  
DQpa/NC  
DQa  
DQa  
NC  
NC  
NC  
1
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
17  
17  
2
AddresQs  
D
array  
A[16:0]  
3
CS  
V
4
register  
DDQ  
V
DDQ  
V
5
SSQ  
NC  
CLK  
6
NC  
7
16/18  
16/18  
DQb  
DQb  
8
9
GWE  
BW  
b
D
Q
V
DDQ  
DQb  
V
10  
11  
SSQ  
SSQ  
V
V
DDQ  
DQb 12  
DQb 13  
Byte Write  
registers  
DQa  
DQa  
VSS  
BWE  
CLK  
FT  
14  
15  
16  
17  
D
Q
TQFP 14 × 20mm  
DQa  
NC  
V
DD  
2
BW  
Byte Write  
registers  
V
ZZ  
NC  
a
DD  
V
SS  
CLK  
DQa  
DQa  
DQb 18  
DQb 19  
CE0  
CE1  
CE2  
OE  
D EnableQ  
register  
Input  
V
SSQ  
V
20  
21  
DDQ  
DDQ  
Output  
V
V
SSQ  
registers  
registers  
DQa  
DQa  
NC  
DQb 22  
DQb 23  
CE  
CLK  
CLK  
CLK  
DQpb/NC  
NC  
24  
25  
26  
27  
28  
29  
30  
NC  
D EnableQ  
delay  
V
DDQ  
V
Power  
down  
SSQ  
SSQ  
ZZ  
V
V
register  
DDQ  
NC  
NC  
NC  
NC  
NC  
NC  
CLK  
OE  
DATA [17:0]  
DATA [15:0]  
FT  
Note: pins 24, 74 are NC for ×16.  
Selection guide  
–200  
5
–183  
–166  
6
–133  
7.5  
133  
4
–100  
10  
Units  
Minimum cycle time  
5.4  
183  
3.1  
540  
140  
30  
ns  
MHz  
ns  
Maximum pipelined clock frequency  
200  
3
166  
3.5  
475  
130  
30  
100  
5
Maximum pipelined clock access time  
Maximum operating current  
570  
160  
30  
425  
100  
30  
325  
90  
mA  
mA  
mA  
Maximum standby current  
Maximum CMOS standby current (DC)  
30  
1/21/02; v.1.1  
Alliance Semiconductor  
P. 1 of 12  
Copyright © Alliance Semiconductor. All rights reserved.  

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