Datasheet > 存储 > SRAM> AS7C33128PFD32B-200TQCN

AS7C33128PFD32B-200TQCN

更新时间： 2024-11-17 22:25:03

品牌	Logo	应用领域
ALSC		内存集成电路静态存储器
页数	文件大小	规格书
19页	553K
描述
3.3V 128K X 32/36 pipeline burst synchronous SRAM

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February 2005

AS7C33128PFD32B

AS7C33128PFD36B

3.3V 128K X 32/36 pipeline burst synchronous SRAM

Features

• Organization: 131,072 words × 32 or 36 bits

• Fast clock speeds to 200 MHz

• Fast clock to data access: 3.0/3.5/4.0 ns

• Fast OE access time: 3.0/3.5/4.0 ns

• Fully synchronous register-to-register operation

• Double-cycle deselect

• Individual byte write and global write

• Multiple chip enables for easy expansion

• 3.3V core power supply

• 2.5V or 3.3V I/O operation with separate V

• Linear or interleaved burst control

• Snooze mode for reduced power-standby

• Common data inputs and data outputs

DDQ

• Asynchronous output enable control

• Available in 100-pin TQFP package

Logic block diagram

LBO

Burst logic

CLK

ADV

ADSC

ADSP

CLK

CLR

128K × 32/36

Memory

array

CLK

A[16:0]

Address

36/32

GWE

BWE

Byte write

registers

CLK

Byte write

registers

CLK

Byte write

registers

CLK

Byte write

registers

CLK

CE0

CE1

CE2

Output

registers

CLK

Input

registers

CLK

Enable

CLK

Enable

delay

CLK

Power

down

36/32

DQ [a:d]

Selection guide

–200

–166

–133

7.5

133

Units

Minimum cycle time

MHz

Maximum clock frequency

Maximum clock access time

Maximum operating current

Maximum standby current

200

3.0

375

130

166

3.5

350

100

325

Maximum CMOS standby current (DC)

1/31/05; v.1.1

Alliance Semiconductor

P. 1 of 19

12 3 4 5 6 7...19

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