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AS7C33128NTF32B-80TQCN

更新时间： 2024-11-01 23:04:23

品牌	Logo	应用领域
ALSC		静态存储器
页数	文件大小	规格书
18页	417K
描述
3.3V 128K x 32/36 Flowthrough Synchronous SRAM with NTD

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April 2005

AS7C33128NTF32B

AS7C33128NTF36B

3.3V 128K × 32/36 Flowthrough Synchronous SRAM with NTD^TM

Features

• Multiple chip enables for easy expansion

• 3.3V core power supply

• 2.5V or 3.3V I/O operation with separate V

• Self-timed write cycles

• Interleaved or linear burst modes

• Snooze mode for standby operation

• Organization: 131,072 words × 32 or 36 bits

™

• NTD architecture for efficient bus operation

DDQ

• Fast clock to data access: 7.5/8.0/10.0 ns

• Fast OE access time: 3.5/4.0 ns

• Fully synchronous operation

• Flow-through mode

• Asynchronous output enable control

• Available in 100-pin TQFP package

• Byte write enables

• Clock enable for operation hold

Logic block diagram

A[16:0]

Address

Burst logic

CLK

CE0

CE1

CE2

Write delay

addr. registers

CLK

R/W

BWa

Control

logic

CLK

BWb

BWc

BWd

ADV / LD

LBO

128K x 32/36

SRAM

CLK

Array

32/36

DQ[a,b,c,d]

Data

Input

32/36

CLK

32/36

CLK

CEN

Output

Buffer

32/36

DQ[a,b,c,d]

Selection guide

-75

-80

-10

Units

Minimum cycle time

8.5

7.5

260

110

Maximum clock access time

Maximum operating current

Maximum standby current

8.0

230

100

200

Maximum CMOS standby current (DC)

4/13/05, v 1.3

Alliance Semiconductor

P. 1 of 18

12 3 4 5 6 7...18

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