Datasheet > AS7C33128NTF18B

AS7C33128NTF18B

更新时间： 2024-10-31 23:04:23

品牌	Logo	应用领域
ALSC		静态存储器
页数	文件大小	规格书
19页	429K
描述
3.3V 128K x 18 Flowthrough Synchronous SRAM with NTD

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数据手册

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AS7C33128NTF18B 数据手册

April 2005

AS7C33128NTF18B

3.3V 128K x 18 Flowthrough Synchronous SRAM with NTD^TM

Features

• Byte write enables

• Clock enable for operation hold

• Multiple chip enables for easy expansion

• 3.3V core power supply

• 2.5V or 3.3V I/O operation with separate V

• Self-timed write cycles

• Organization: 131,072 words × 18 bits

™

• NTD architecture for efficient bus operation

• Fast clock to data access: 7.5/8.0/10.0 ns

• Fast OE access time: 3.5/4.0 ns

• Fully synchronous operation

DDQ

• Interleaved or linear burst modes

• Snooze mode for standby operation

• Flow-through mode

• Asynchronous output enable control

• Available in 100-pin TQFP package

Logic block diagram

A[16:0]

Address

burst logic

CLK

CE0

CE1

CE2

Write delay

addr. registers

CLK

R/W

BWa

BWb

Control

logic

CLK

ADV / LD

128K x 18

LBO

SRAM

array

CLK

DQ [a,b]

Data

input

CLK

CEN

Output

buffer

DQ [a,b]

Selection guide

-75

8.5

7.5

260

110

-80

-10

Units

Minimum cycle time

8.0

230

100

Maximum clock access time

Maximum operating current

Maximum standby current

200

Maximum CMOS standby current (DC)

4/28/05, v 1.0

Alliance Semiconductor

P. 1 of 19

12 3 4 5 6 7...19

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