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AS7C33128NTD36B-133TQIN

更新时间： 2024-10-31 23:04:23

品牌	Logo	应用领域
ALSC		静态存储器
页数	文件大小	规格书
18页	435K
描述
3.3V 128Kx32/36 Pipelined SRAM with NTD

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February 2005

AS7C33128NTD32B

AS7C33128NTD36B

3.3V 128K×32/36 Pipelined SRAM with NTD^TM

Features

• Clock enable for operation hold

• Multiple chip enables for easy expansion

• 3.3V core power supply

• 2.5V or 3.3V I/O operation with separate V_DDQ

• Self-timed write cycles

• Organization: 131,072 words × 32 or 36 bits

• NTD^™architecture for efficient bus operation

• Fast clock speeds to 200 MHz

• Fast clock to data access: 3.0/3.5/4.0 ns

• Fast OE access time: 3.0/3.5/4.0 ns

• Fully synchronous operation

• Asynchronous output enable control

• Available in 100-pin TQFP package

• Byte write enables

• Interleaved or linear burst modes

• Snooze mode for reduced power standby

Logic block diagram

^DAddress

Burst logic

A[16:0]

CLK

CE0

CE1

CE2

Write delay

addr. registers

CLK

R/W

BWa

BWb

BWc

BWd

Control

logic

CLK

ADV / LD

128K x 32/36

SRAM

Array

LBO

CLK

32/36

Data

DQ [a:d]

Input

CLK

32/36

CLK

CEN

CLK

Output

32/36

DQ [a:d]

Selection Guide

-200

-166

-133

7.5

133

Units

Minimum cycle time

Maximum clock frequency

Maximum clock access time

Maximum operating current

Maximum standby current

200

3.0

375

135

166

3.5

350

120

MHz

325

110

Maximum CMOS standby current (DC)

2/8/05; v.1.5

Alliance Semiconductor

P. 1 of 18

12 3 4 5 6 7...18

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