March 2002
AS7C33128NTD32A
AS7C33128NTD36A
&
TM
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Features
™1
• Economical 100-pin TQFP package
• Byte write enables
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V
• 30 mW typical standby power
• Self-timed write cycles
• Organization: 131,072 words × 32 or 36 bits NTD
architecture for efficient bus operation
• Fast clock speeds to 200 MHz in LVTTL/LVCMOS
• Fast clock to data access: 3.0/3.1/3.5/4.0/5.0 ns
• Fast OE access time: 3.0/3.1/3.5/4.0/5.0 ns
• Fully synchronous operation
DDQ
• “Flow-through” or “pipelined” mode
• Asynchronous output enable control
• Interleaved or linear burst modes
• Snooze mode for standby operation
™
1. NTD is a trademark of Alliance Semiconductor Corporation.
Pin arrangement for TQFP (top view)
Logic block diagram
17
17
Q
D Address
register
Burst logic
A[16:0]
17
17
CLK
D
Q
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPc, NC
DQc
DQPb, NC
DQb
CE0
CE1
Write delay
2
17
addr. registers
CLK
3
CE2
DQc
DQb
4
V
V
V
DDQ
SSQ
DDQ
SSQ
R/W
BWa
BWb
BWc
BWd
5
V
Control
logic
6
DQc
DQc
DQc
DQc
DQb
DQb
DQb
DQb
CLK
7
8
9
ADV / LD
FT
128K x 32/36
SRAM
Array
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
V
V
DQb
DQb
SSQ
SSQ
DDQ
V
DDQ
CLK
LBO
ZZ
DQc
DQc
FT
TQFP 14x20mm
V
SS
V
V
32/36
32/36
DD
DD
SS
DD
DD
Data
Input Q
DQ [a:d]
D
V
V
V
DQd
DQd
ZZ
Register
CLK
32/36
32/36
DQa
DQa
V
V
V
DDQ
SSQ
DDQ
SSQ
V
DQd
DQa
DQa
DQa
DQa
32/36
DQd
DQd
DQd
CLK
CEN
CLK
V
V
Output
Register
SSQ
SSQ
DDQ
DQa
V
DQd
DQd
V
DDQ
OE
DQa
DQPd, NC
DQPa, NC
32/36
OE
DQ [a:d]
Note: Pins 1,30,51,80 are NC for ×32
Selection Guide
-200
-183
-166
6
-133
7.5
133
4
-100
10
Units
ns
Minimum cycle time
5.0
200
3.0
570
160
30
5.4
183
3.1
540
140
30
Maximum pipelined clock frequency
Maximum pipelined clock access time
Maximum operating current
166
3.5
475
130
30
100
5
MHz
ns
425
100
30
325
90
mA
mA
mA
Maximum standby current
Maximum CMOS standby current (DC)
30
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