Datasheet > 存储 > SRAM> AS7C33128FT36B-80TQCN

AS7C33128FT36B-80TQCN

更新时间： 2024-10-31 23:04:23

品牌	Logo	应用领域
ALSC		存储内存集成电路静态存储器时钟
页数	文件大小	规格书
19页	417K
描述
3.3V 128K x 32/36 Flow Through Synchronous SRAM

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AS7C33128FT36B-80TQCN 数据手册

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AS7C33128FT32B

AS7C33128FT36B

February 2005

3.3V 128K × 32/36 Flow Through Synchronous SRAM

Features

• Multiple chip enables for easy expansion

• 3.3V core power supply

• Organization: 131,072 words × 32 or 36 bits

• Fast clock to data access: 6.5/7.5/8.0/10.0 ns

• Fast OE access time: 3.5/4.0 ns

• Fully synchronous flow through operation

• Asynchronous output enable control

• Available in 100-pin TQFP package

• Individual byte write and Global write

• 2.5V or 3.3V I/O operation with separate V

• Linear or interleaved burst control

• Snooze mode for reduced power standby

• Common data inputs and data outputs

DDQ

Logic block diagram

LBO

CLK

ADV

CLK

Burst logic

ADSC

ADSP

CLR

128K × 32/36

Memory

array

CLK

[18:0]

Address

36/32

GWE

BWE

BW_d

DQ_d

Byte write

registers

CLK

DQ_c

Byte write

registers

BW_c

BW_b

BW_a

CLK

DQ_b

Byte write

registers

CLK

DQ_a

Byte write

registers

CLK

CE0

CE1

Output

buffer

CE2

Input

registers

CLK

Enable

CLK

Enable

Power

down

delay

CLK

36/32

DQ[a:d]

Selection guide

–65

-75

8.5

7.5

250

-80

-10

Units

Minimum cycle time

7.5

6.5

275

Maximum clock access time

Maximum operating current

Maximum standby current

8.0

215

10.0

185

Maximum CMOS standby current (DC)

2/8/05; v.1.2

Alliance Semiconductor

P. 1 of 19

12 3 4 5 6 7...19

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