Datasheet > 存储 > SRAM> AS7C33128FT18B-65TQC

AS7C33128FT18B-65TQC

更新时间： 2024-11-26 22:24:39

品牌	Logo	应用领域
ALSC		存储内存集成电路静态存储器时钟
页数	文件大小	规格书
19页	399K
描述
3.3V 128K x 18 Flow Through Synchronous SRAM

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AS7C33128FT18B-65TQC 数据手册

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AS7C33128FT18B

December 2004

3.3V 128K × 18 Flow Through Synchronous SRAM

Features

• 3.3V core power supply

• Organization: 131,072 words × 18 bits

• Fast clock to data access: 6.5/7.5/8.0/10.0 ns

• Fast OE access time: 3.5/4.0 ns

• Fully synchronous flow through operation

• Asynchronous output enable control

• Economical 100-pin TQFP package

• Individual byte write and Global write

• Multiple chip enables for easy expansion

• 2.5V or 3.3V I/O operation with separate V

• Linear or interleaved burst control

• Snooze mode for reduced power standby

• Common data inputs and data outputs

DDQ

Logic block diagram

LBO

CLK

ADV

CLK

CLR

Burst logic

128K × 18

Memory

array

ADSC

ADSP

A[16:0]

Address

CLK

GWE

DQb

Byte Write

registers

CLK

BWE

DQa

Byte Write

registers

CLK

CE0

CE1

Output

Buffers

Input

registers

Enable

CE2

CLK

Enable

delay

Power

down

CLK

DQ [a,b]

Selection guide

–65

7.5

6.5

250

120

-75

8.5

7.5

225

100

-80

-10

Units

Minimum cycle time

Maximum clock access time

Maximum operating current

Maximum standby current

8.0

200

10.0

175

Maximum CMOS standby current (DC)

12/10/04; v.1.3

Alliance Semiconductor

P. 1 of 19

12 3 4 5 6 7...19

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