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AS7C33128FT18B-10TQC PDF预览

AS7C33128FT18B-10TQC

更新时间: 2024-10-31 22:24:39
品牌 Logo 应用领域
ALSC 存储内存集成电路静态存储器
页数 文件大小 规格书
19页 399K
描述
3.3V 128K x 18 Flow Through Synchronous SRAM

AS7C33128FT18B-10TQC 数据手册

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AS7C33128FT18B  
December 2004  
®
3.3V 128K × 18 Flow Through Synchronous SRAM  
Features  
• 3.3V core power supply  
• Organization: 131,072 words × 18 bits  
• Fast clock to data access: 6.5/7.5/8.0/10.0 ns  
• Fast OE access time: 3.5/4.0 ns  
• Fully synchronous flow through operation  
• Asynchronous output enable control  
• Economical 100-pin TQFP package  
• Individual byte write and Global write  
• Multiple chip enables for easy expansion  
• 2.5V or 3.3V I/O operation with separate V  
• Linear or interleaved burst control  
• Snooze mode for reduced power standby  
• Common data inputs and data outputs  
DDQ  
Logic block diagram  
LBO  
CLK  
ADV  
CLK  
CS  
CLR  
Burst logic  
128K × 18  
Memory  
array  
ADSC  
ADSP  
2
2
17  
Q
D
A[16:0]  
Address  
17  
CS  
15  
17  
register  
CLK  
18  
18  
GWE  
D
Q
DQb  
BW  
b
Byte Write  
registers  
CLK  
BWE  
D
Q
DQa  
2
BW  
Byte Write  
a
registers  
CLK  
CE0  
CE1  
OE  
Output  
Buffers  
D
Q
Q
Input  
registers  
Enable  
register  
CE2  
CE  
CLK  
CLK  
D
Enable  
delay  
register  
Power  
down  
ZZ  
CLK  
OE  
18  
DQ [a,b]  
Selection guide  
–65  
7.5  
6.5  
250  
120  
30  
-75  
8.5  
7.5  
225  
100  
30  
-80  
10  
-10  
12  
Units  
Minimum cycle time  
ns  
ns  
Maximum clock access time  
Maximum operating current  
Maximum standby current  
8.0  
200  
90  
10.0  
175  
90  
mA  
mA  
mA  
Maximum CMOS standby current (DC)  
30  
30  
12/10/04; v.1.3  
Alliance Semiconductor  
P. 1 of 19  
Copyright © Alliance Semiconductor. All rights reserved.  

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