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AS7C3256PFS16A-3.8TQC PDF预览

AS7C3256PFS16A-3.8TQC

更新时间: 2024-11-01 15:27:59
品牌 Logo 应用领域
ALSC 时钟静态存储器内存集成电路
页数 文件大小 规格书
11页 158K
描述
Standard SRAM, 256KX16, 3.8ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100

AS7C3256PFS16A-3.8TQC 数据手册

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April 2000  
Advance information  
AS7C3256PFS16A  
AS7C3256PFS18A  
®
3.3V 256K × 16/ 18 pipeline burst synchronous SRAM  
Synchronous and asynchronous output enable control  
Economical 100-pin TQFP package  
Byte write enables  
Clock enable for operation hold  
• Multiple chip enables for easy expansion  
• 3.3V core power supply  
• Organization: 262,144 words × 16 or 18 bits  
Fast clock speeds to 166 MHz in LVTTL/ LVCMOS  
Fast clock to data access: 3.5/ 3.8/ 4/ 5 ns  
Fast OEaccess time: 3.5/ 3.5/ 3.8/ 5.0 ns  
Fully synchronous register-to-register operation  
• “Flow-through” mode  
Single-cycle deselect  
- Double-cycle deselect also available (AS7C3256PFD16A/  
AS7C3256PFD18A)  
• 2.5V or 3.3V I/ O operation with separate V  
DDQ  
Automatic power down: 30 mW typical standby power  
• NTD™ pipeline architecture available  
(AS7C3256NTD16A/ AS7C3256NTD18A)  
Pentium® compatible architecture and timing  
LBO  
CLK  
ADV  
ADSC  
CLK  
CE  
Burst logic  
256K×32/ 36  
Memory  
CLR  
ADSP  
A
18  
16  
18  
NC  
NC  
NC  
1
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
18  
D
Address Q  
A[17:0]  
array  
2
NC  
NC  
V
CE  
CLK  
3
register  
V
4
DDQ  
DDQ  
V
V
5
SSQ  
SSQ  
NC  
NC  
6
36/ 32  
36/ 32  
GWE  
BWE  
DQpa/ NC  
DQa  
NC  
DQb  
DQb  
7
D
Q
Q
Q
Q
DQd  
8
BW  
d
Byte Write  
CLK  
DQa  
9
registers  
V
V
10  
11  
12  
13  
SSQ  
SSQ  
V
V
DDQ  
DDQ  
D
DQa  
DQa  
DQb  
DQc  
BW  
c
DQb  
Byte Write  
CLK  
V
FT 14  
SS  
registers  
TQFP 14×20mm  
NC  
V
15  
DD  
V
NC 16  
DD  
D
ZZ  
V
17  
18  
19  
20  
21  
22  
23  
SS  
DQb  
BW  
b
DQb  
DQb  
DQa  
DQa  
Byte Write  
CLK  
registers  
V
V
DDQ  
CCQ  
V
V
SSQ  
SSQ  
D
DQa  
DQa  
NC  
DQb  
DQa  
BW  
4
a
DQb  
Byte Write  
CLK  
registers  
DQpb/ NC 24  
NC 25  
NC  
CE0  
CE1  
CE2  
V
V
26  
27  
SSQ  
SSQ  
D
Q
Q
OE  
V
V
DDQ  
DDQ  
Enable  
Output  
Input  
registers  
CLK  
NC  
NC  
NC  
NC 28  
NC 29  
NC 30  
CE register  
CLK  
registers  
CLK  
LE  
FT  
D
Enable  
Power  
down  
ZZ  
delay  
register  
CLK  
Note: pins 24, 74 are NC for ×16.  
36/ 32  
DATA [35:0]  
[31:0]  
OE  
AS7C3256PFS16A- AS7C3256PFS16A- AS7C3256PFS16A- AS7C3256PFS16A-  
3.5  
3.8  
6.7  
150  
3.8  
400  
60  
4
7.5  
133.3  
4
5
10  
100  
5
Units  
ns  
Minimum cycle time  
6
Maximum pipelined clock frequency  
Maximum pipelined clock access time  
Maximum operating current  
166.7  
3.5  
450  
60  
MHz  
ns  
350  
60  
300  
60  
5
mA  
mA  
mA  
Maximum standby current  
Maximum CMOS standby current (DC)  
5
5
5
NTD™ is a trademark of Alliance Semiconductor Corporation  
Pentium® is a registered trademark of Intel Corporation.  
DID 11-20027-A. 6/ 8/ 00  
ALLIANCE SEMICONDUCTOR  
1

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